Abstract: A semiconductor device according to the present embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer. A gate electrode is provided on the semiconductor layer via the gate dielectric film. A drain layer of a first conductivity type is provided in a part of the semiconductor layer on a side of a first end of the gate electrode. A source layer of a second conductivity type is provided in a part of the semiconductor layer on a side of a second end of the gate electrode and below the gate electrode. The source layer has a substantially uniform impurity concentration at the part of the semiconductor layer below the gate electrode. Voltages of a same polarity are applied to the gate electrode and the drain layer.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors of first and second conductivity types on the substrate. The first transistor includes a first gate electrode on the substrate, a first source region of the second conductivity type and a first drain region of the first conductivity type disposed to sandwich the first gate electrode, and a first channel region of the first or second conductivity type disposed between the first source region and the first drain region. The second transistor includes a second gate electrode on the substrate, a second source region of the first conductivity type and a second drain region of the second conductivity type disposed to sandwich the second gate electrode, and a second channel region disposed between the second source region and the second drain region and having the same conductivity type as the first channel region.

Abstract: A semiconductor device includes a semiconductor layer opposing to a bottom surface and a side surface of a gate electrode. An insulation film is provided between the bottom surface of the gate electrode and the semiconductor layer and between the side surface of the gate electrode and the semiconductor layer. A first conduction-type drain layer is provided in the semiconductor layer on a side of an end part of one of the bottom surface and the side surface of the gate electrode. A second conduction-type source layer is provided in the semiconductor layer opposing to the other one of the bottom surface and the side surface of the gate electrode. A second conduction-type extension layer is provided in the semiconductor layer opposing to a corner part between the side surface and the bottom surface of the gate electrode and has a lower impurity concentration than that of the source layer.

Abstract: A semiconductor device according to the present embodiment includes a semiconductor layer. A gate dielectric film is provided on a surface of the semiconductor layer. A gate electrode is provided on the semiconductor layer via the gate dielectric film. A drain layer of a first conductivity type is provided in a part of the semiconductor layer on a side of a first end of the gate electrode. A source layer of a second conductivity type is provided in a part of the semiconductor layer on a side of a second end of the gate electrode and below the gate electrode. The source layer has a substantially uniform impurity concentration at the part of the semiconductor layer below the gate electrode. Voltages of a same polarity are applied to the gate electrode and the drain layer.

Abstract: In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer of the second conductivity type coming in contact with the first and second element isolation insulator films and having an upper surface in a position deeper than lower surfaces of the first and second main terminal regions, a first well region of the first conductivity type formed between the first main terminal region and the diffusion layer, and a second well region of the first conductivity type formed between the second main terminal region and the diffusion layer. The second well region has a impurity concentration higher than that of the first well region.

Abstract: According to one embodiment, a MOS semiconductor device comprises a first gate insulating film formed on a region of part of a channel of a semiconductor substrate, in which a transistor is to be formed, a first gate electrode formed on the first gate insulating film, a second gate insulating film formed on remaining part of the channel, the second gate insulating film including an impurity added to the second gate insulating film to increase a threshold value of the channel immediately under the second gate insulating film, and a second gate electrode formed on the second gate insulating film.

Abstract: According to one embodiment, a semiconductor device includes a gate electrode formed on a substrate with a gate insulation film interposed therebetween, and a source region of a first conductivity type and a drain region of a second conductivity type reverse to the first conductivity type, which are formed so as to hold the gate electrode therebetween within the substrate. The work function of a first region on the source region side within the gate electrode is shifted toward the first conductivity type as compared to the work function of a second region on the drain region side within the gate electrode.

Abstract: According to one embodiment, a semiconductor device includes a gate electrode formed on a substrate with a gate insulation film interposed therebetween, and a source region of a first conductivity type and a drain region of a second conductivity type reverse to the first conductivity type, which are formed so as to hold the gate electrode therebetween within the substrate. The work function of a first region on the source region side within the gate electrode is shifted toward the first conductivity type as compared to the work function of a second region on the drain region side within the gate electrode.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. Two or more layers can be formed on a silicon substrate, wherein one or more of the layers are used for controlling an isolation recess. A first layer can comprise a first material and a second layer can comprise a second material.

Abstract: A semiconductor substrate according to one embodiment includes: a first transistor having a first gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the first gate insulating film and a first sidewall formed on a side face of the first gate electrode, the first gate insulating film comprising a high-dielectric constant material as a base material, a part of the first sidewall contacting with the first gate insulating film and containing Si and N; and a second transistor having a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film and a second sidewall formed on a side face of the second gate electrode so as to contact with the second gate insulating film, the second gate insulating film comprising a high-dielectric constant material as a base material, a part of the second sidewall contacting with the second gate insulating film and containing Si and N, wherein at least one of an abundance

Abstract: Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device, having more than two types of threshold voltages, can be employed in a logic integrated circuit with an embedded SRAM. The semiconductor device can include at least two transistors. The two transistors can be the same conductivity type (e.g., n-type or p-type). In addition, the two transistors can have disparate voltage thresholds.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having first and second regions; a first transistor comprising a first gate insulating film and a first gate electrode thereon in the first region on the semiconductor substrate, the first gate insulating film comprising a first interface layer containing nitrogen atoms and a first high dielectric constant layer thereon; a second transistor comprising a second gate insulating film and a second gate electrode thereon in the second region on the semiconductor substrate, the second gate insulating film comprising a second interface layer and a second high dielectric constant layer thereon, the second interface layer containing nitrogen atoms at an average concentration lower than that of the first interface layer or not containing nitrogen atoms, and the second transistor having a threshold voltage different from that of the first transistor; and an element isolation region on the semiconductor substrate, the element isolation

Abstract: A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same const

Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; an element isolation region provided in the semiconductor substrate and having an oxide layer and an oxidant-diffusion prevention layer provided on the oxide layer; a gate dielectric film provided on the semiconductor substrate and the oxidant-diffusion prevention layer; and a gate electrode provided on the gate dielectric film.

Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; an element isolation region provided in the semiconductor substrate and having an oxide layer and an oxidant-diffusion prevention layer provided on the oxide layer; a gate dielectric film provided on the semiconductor substrate and the oxidant-diffusion prevention layer; and a gate electrode provided on the gate dielectric film.

Abstract: A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.

Abstract: A semiconductor device according to an embodiment includes: a fin type MOSFET having a first gate electrode, and a first gate insulating film for generating Fermi level pinning in the first gate electrode; and a planar type MOSFET having a second gate electrode, and a second gate insulating film for generating no Fermi level pinning in the second gate electrode, or generating Fermi level pinning weaker than that generated in the first gate electrode in the second gate electrode.

Abstract: A semiconductor substrate according to one embodiment includes: a first transistor having a first gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the first gate insulating film and a first sidewall formed on a side face of the first gate electrode, the first gate insulating film comprising a high-dielectric constant material as a base material, a part of the first sidewall contacting with the first gate insulating film and containing Si and N; and a second transistor having a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film and a second sidewall formed on a side face of the second gate electrode so as to contact with the second gate insulating film, the second gate insulating film comprising a high-dielectric constant material as a base material, a part of the second sidewall contacting with the second gate insulating film and containing Si and N, wherein at least one of an abundance

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having first and second regions; a first transistor comprising a first gate insulating film and a first gate electrode thereon in the first region on the semiconductor substrate, the first gate insulating film comprising a first interface layer containing nitrogen atoms and a first high dielectric constant layer thereon; a second transistor comprising a second gate insulating film and a second gate electrode thereon in the second region on the semiconductor substrate, the second gate insulating film comprising a second interface layer and a second high dielectric constant layer thereon, the second interface layer containing nitrogen atoms at an average concentration lower than that of the first interface layer or not containing nitrogen atoms, and the second transistor having a threshold voltage different from that of the first transistor; and an element isolation region on the semiconductor substrate, the element isolation