Patents by Inventor Masakazu Goto

Masakazu Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100072554
    Abstract: A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same const
    Type: Application
    Filed: August 13, 2009
    Publication date: March 25, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Goto, Shigeru Kawanaka
  • Publication number: 20090267159
    Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.
    Type: Application
    Filed: February 19, 2009
    Publication date: October 29, 2009
    Inventors: Kosuke Tstsumura, Masakazu Goto, Reika Ichihara, Masato Koyama, Shigeru Kawanaka, Kazuaki Nakajima
  • Publication number: 20090224329
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; an element isolation region provided in the semiconductor substrate and having an oxide layer and an oxidant-diffusion prevention layer provided on the oxide layer; a gate dielectric film provided on the semiconductor substrate and the oxidant-diffusion prevention layer; and a gate electrode provided on the gate dielectric film.
    Type: Application
    Filed: March 5, 2009
    Publication date: September 10, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Masakazu GOTO
  • Publication number: 20090152623
    Abstract: A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 18, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu GOTO, Nobutoshi AOKI, Takashi IZUMIDA, Kimitoshi OKANO, Satoshi INABA, Ichiro MIZUSHIMA
  • Publication number: 20090008716
    Abstract: A semiconductor device according to an embodiment includes: a fin type MOSFET having a first gate electrode, and a first gate insulating film for generating Fermi level pinning in the first gate electrode; and a planar type MOSFET having a second gate electrode, and a second gate insulating film for generating no Fermi level pinning in the second gate electrode, or generating Fermi level pinning weaker than that generated in the first gate electrode in the second gate electrode.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 8, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu GOTO, Makoto Fujiwara
  • Publication number: 20080258244
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a gate dielectric layer provided on the semiconductor substrate, a source region provided in the semiconductor substrate, a drain region provided in the semiconductor substrate, and a gate electrode provided on the gate dielectric layer having a metal containing layer and a polycrystalline silicon layer having an impurity ion, the polycrystalline silicon layer provided on the metal containing layer so as to cover an upper surface and side surface of the metal containing layer.
    Type: Application
    Filed: January 18, 2008
    Publication date: October 23, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu GOTO, Shigeru KAWANAKA
  • Patent number: 4892387
    Abstract: The present invention is directed to a light controlling sheet in use for optical indicators which comprises louver elements including an arbitrary pattern of walls which are parallel to each other and so opaque as to absorb incident light; transparent layers for permitting the incident light to pass therethrough and light reflection layers for reflecting the incident light. The transparent layers and the light reflection layers are mutually interposed between the walls of the louver element. The oblique light from the light source strikes the side surfaces of the walls, while the substantially parallel light from the light source passes through the transparent layers toward the observer. The extraneous light is reflected at the front surface of the light reflection layers so that the light controlling sheet is bright and stands out clearly.
    Type: Grant
    Filed: July 20, 1988
    Date of Patent: January 9, 1990
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Noboru Takeuchi, Masakazu Goto, Hiroaki Takahashi, Takeshi Kojima
  • Patent number: 4788094
    Abstract: The disclosure relates to a light controlling sheet for use with indicators which includes a louver element including an arbitrary pattern of walls which are parallel to each other and opaque so as to absorb light, and an electrically conductive film which is mounted on one surface of the louver element. This film is porous so that the light from a light source may penetrate. The oblique light strikes the opaque walls of the louver element and is absorbed in the walls, while the substantially parallel light is permitted to pass through the space or transparent portion betwee the walls. The electrically conductive film not only acts as a protective cover for the louver element but also shields unwanted electromagnetic wave.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: November 29, 1988
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Masayuki Morita, Noboru Takeuchi, Masakazu Goto, Hiroaki Takahashi, Takeshi Kojima
  • Patent number: 4772097
    Abstract: The present invention is directed to a light controlling sheet in use for optical indicators which comprises louver elements including an arbitrary pattern of walls which are parallel to each other and so opaque as to absorb incident light; transparent layers for permitting the incident light to pass therethrough and light reflection layers for reflecting the incident light. The transparent layers and the light reflection layers are mutually interposed between the walls of the louver element. The oblique light from the light souce strikes the side surfaces of the walls, while the substantially parallel light from the light source passes through the transparent layers toward the observer. The extraneous light is reflected at the front surface of the light reflection layers so that the light controlling sheet is bright and stands out clearly.
    Type: Grant
    Filed: October 15, 1986
    Date of Patent: September 20, 1988
    Assignee: Kabushiki Kaisha Tokai Rika
    Inventors: Noboru Takeuchi, Masakazu Goto, Hiroaki Takahashi, Takeshi Kojima