Abstract: Provided is a piezoelectric ceramic composition which enables the attainment of sufficiently high Qmax and good temperature characteristics of oscillation frequency F0 when applied in an oscillator utilizing third harmonic mode of thickness longitudinal vibration. The piezoelectric ceramic composition contains a composite oxide having a perovskite structure. The composite oxide has a composition expressed by the chemical formula (1), while satisfying 0.91???1.00, 0<??0.08, 0.125?x?0.300, 0.020?y?0.050, and 0.040?z?0.070 (Pb?Ln?)(Ti1?(x+y+z)ZrxMnyNbz)O3 ??(1) where Ln signifies at least one element selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

Abstract: There are provided steps of polarizing a ceramic composition including a perovskite compound containing Pb, Zr, Ti and Mn as main components and a heat treatment step for keeping the polarized ceramic composition within a temperature range lower than Tc (Tc denoting the Curie temperature of the ceramic composition) for 1 to 100 minutes.

Abstract: There is provided a resonator having a piezoelectric ceramic resonator which has excellent free-fall resistance. The resonator comprises a piezoelectric ceramic resonator 2 with a vibrating electrode formed, and a substrate 3 which supports the piezoelectric ceramic resonator 2, wherein the piezoelectric ceramic resonator 2 satisfies the condition of U?0.88×H+20.28, wherein U=maximum elastic energy (kJ/m3) per unit volume, and H=drop height (m) (H>1). The present invention can be applied to a resonator 1, wherein the substrate 3 has terminal electrodes 31, 32, and the piezoelectric ceramic resonator 2 is in electrical continuity with the vibrating electrode and is supported on the substrate 3 at both ends via a conductive stator 4.

Abstract: Provided is a piezoelectric ceramic composition which enables the attainment of sufficiently high Qmax and good temperature characteristics of oscillation frequency F0 when applied in an oscillator utilizing third harmonic mode of thickness longitudinal vibration. The piezoelectric ceramic composition contains a composite oxide having a perovskite structure. The composite oxide has a composition expressed by the chemical formula (1), while satisfying 0.91???1.00, 0<??0.08, 0.125?x?0.300, 0.020?y?0.050, and 0.040?z?0.070. (Pb?Ln?)(Ti1?(x+y+z)ZrxMnyNbz)O3 ??(1) where Ln signifies at least one element selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Th, Dy, Ho, Er, Tm, Yb, and Lu.

Abstract: To provide a method for producing a piezoelectric ceramic which can improve toughness thereof. Provided is a method for producing a piezoelectric ceramic which includes a step of polarizing a piezoelectric ceramic having a main component represented by a composition formula Pba[(MnbNbc)dTieZrf]O3, wherein a to f satisfy 0.98?a?1.01, 0.340?b?0.384, 0.616?c?0.660, 0.08?d?0.12, 0.500?e?0.540, 0.37?f?0.41, and bd+cd+e+f=1, and 1 to 10% by weight of Al in terms of Al2O3 as an additive, and heat-treating the polarized piezoelectric ceramic for 10 to 60 minutes in a range of 200 to 300° C. As a result of this heat treatment, toughness of the piezoelectric ceramic can be improved.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: To obtain a piezoelectric ceramic composition having extremely high heat resisting property. Provided is a piezoelectric ceramic composition comprising a main component represented by Pba[(MnbNbc)dTieZrf]O3 (wherein 0.98?a?1.01, 0.340?b?0.384, 0.616?c?0.660, 0.08?d?0.12, 0.500?e?0.540, 0.37?f?0.41, bd+cd+e+f=1), and 1 to 10% by weight of Al in terms of Al2O3 as an additive. Preferably, b is such that 0.345?b?0.375 and c is such that 0.625?c?0.655, and the Al as the additive is preferably 2 to 6% by weight in terms of Al2O3.

Abstract: A piezoelectric ceramic composition excellent in all of the electric property Qmax, heat resisting properties and temperature characteristics of oscillation frequencies is provided. The piezoelectric ceramic composition comprises a phase mainly comprising lead zirconate titanate having a perovskite structure and an Al-containing phase. In the piezoelectric ceramic composition, the main component preferably comprises Mn and Nb, and is preferably represented by a composition formula of Pb?[(Mn1/3Nb2/3)xTiyZrz]O3 (wherein 0.97???1.01, 0.04?x?0.16, 0.48?y?0.58, 0.32?z?0.41).

Abstract: The present invention has an object to provide piezoelectric ceramics containing no lead, having a high Curie point, and further, having excellent piezoelectric properties, particularly large Qmax. The piezoelectric ceramics contain, as a main component, a bismuth layer-structured compound having (MII1-xLnx)Bi4Ti4O15 crystals (MII is an element selected from Sr, Ba, and Ca, Ln is an element selected from lanthanoids, and x is within a range of 0<x?0.5) and further contain, as secondary components, at least one of Mn oxide and Co oxide, and lanthanoid, wherein the lanthanoid being the secondary component is contained within a range of 0.02 to 0.12 wt % in terms of oxide thereof.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: A piezoelectric ceramics having ceramic particles, wherein said ceramic particles comprises bismuth layer compound containing at least Sr, Ln (note that Ln is a lanthanoid element), Bi, Ti and O and including MIIBi4Ti4O15 type crystal (MII is an element composed of Sr and Ln) as a main component, and an oxide of Mn as a subcomponent; and an average particle diameter by the code length measuring method is 0.8 to 4.7 ?m: by which it is possible to provide piezoelectric ceramics having a large Qmax in a third harmonic mode of thickness vertical vibration in a relatively high frequency band (for example, 16 to 65 MHz), a resonator an other piezoelectric element comprising the piezoelectric ceramics as a piezoelectric substance thereof.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: A piezoelectric ceramic composition excellent in heat resisting properties is provided. In the piezoelectric ceramic composition including a perovskite compound containing Pb, Zr and Ti as main components, the piezoelectric ceramic composition is made to include Cr as an additive from 0.025 to 0.250 wt % in terms of Cr2O3. In the piezoelectric ceramic composition of the present invention, ?k15 (here, ?k15 is the rate of change in electromechanical coupling factor k15, caused by external thermal shock), of the piezoelectric ceramic composition can be controlled to 3.0% or less in absolute value.

Abstract: There is provided a resonator having a piezoelectric ceramic resonator which has excellent free-fall resistance. The resonator comprises a piezoelectric ceramic resonator 2 with a vibrating electrode formed, and a substrate 3 which supports the piezoelectric ceramic resonator 2, wherein the piezoelectric ceramic resonator 2 satisfies the condition of U?0.88×H+20.28, wherein U=maximum elastic energy (kJ/m3) per unit volume, and H=drop height (m) (H>1). The present invention can be applied to a resonator 1, wherein the substrate 3 has terminal electrodes 31, 32, and the piezoelectric ceramic resonator 2 is in electrical continuity with the vibrating electrode and is supported on the substrate 3 at both ends via a conductive stator 4.

Abstract: The present invention has an object to provide piezoelectric ceramics containing no lead, having a high Curie point, and further, having excellent piezoelectric properties, particularly large Qmax. The piezoelectric ceramics contain, as a main component, a bismuth layer-structured compound having (MII1-xLnx)Bi4Ti4O15 crystals (MII is an element selected from Sr, Ba, and Ca, Ln is an element selected from lanthanoids, and x is within a range of 0<x?0.5) and further contain, as secondary components, at least one of Mn oxide and Co oxide, and lanthanoid, wherein the lanthanoid being the secondary component is contained within a range of 0.02 to 0.12 wt % in terms of oxide thereof.

Abstract: A piezoelectric ceramic composition which has a large electromechanical coupling factor and is excellent in heat resisting properties is provided. As additives, Cr, Al and Si are contained together in the piezoelectric ceramic composition including a perovskite compound which contains Pb, Zr and Ti as main components. Preferably, Cr, Al and Si are respectively contained in a content of 0.05 to 0.50 wt % in terms of Cr2O3, in a content of 0.005 to 1.500 wt % in terms of Al2O3, and in a content of 0.005 to 0.100 wt % in terms of SiO2. By simultaneously including these three elements and setting the contents thereof to fall within the above mentioned ranges, the electromechanical coupling factor kt can be 30% or more, and ?Fr, which is the rate of change in resonant frequency Fr between before and after application of an external thermal shock, can be 0.5% or less in absolute value.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.