Abstract: The semiconductor memory device has a word configuration determination signal generating circuit including a plurality of generating circuits, each of which is formed of two clocked inverters and two inverters. In a normal operation mode, a test mode signal TX4 is inactivated and a word configuration determination signal [x16E] of an H level is output. In a test mode, the test mode signal TX4 is activated and a word configuration determination signal [x4E] of an H level is output. Thus, in the test mode, the word configuration is switched to the one that is smaller than in the normal operation mode. This allows simultaneous testing of a larger number of semiconductor memory devices.

Abstract: Piezoelectric ceramics include a bismuth layer compound containing MII, Bi, Ti, Ln and O, wherein MII represents at least one element selected from the group consisting of Sr, Ba and Ca, and Ln represents at least one element selected from the group consisting of lanthanoids. The piezoelectric ceramics include MIIBi4Ti4O15 typed crystals, and a mole ratio of Ln/(Ln+MII) is 0<Ln/(Ln+MII)<0.5. In the case where MII is Sr, a mole ratio of 4Bi/Ti is 4.000<4Bi/Ti≦4.030. Preferably, piezoelectric ceramics further include Y oxide.

Abstract: Piezoelectric ceramics which is made of compounds shaped in bismuth layer containing Sr, Bi, Ti and Ln (lanthanoid). The compound contains SrBi4Ti4O15 typed crystals. In the piezoelectric ceramics, an atomic ratio of Ln/(Sr+Ln) is 0<Ln/(Sr+Ln)<0.5.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: A lead-oxide-free piezoelectric ceramic composition having an electromechanical coupling coefficient greater than a predetermined value and having a Curie point of at least 500.degree. C., whose main component is a two-component-based solid solution of the formula of (1-x)Bi.sub.a Ti.sub.b Nb.sub.c O.sub.9 -xNa.sub.p Bi.sub.q Nb.sub.r O.sub.9, and which has a bismuth layer structure in the range of 0<x<1,the solid solution of the above formula satisfying 2.4<(1-x)a+xq<3.1,0<b<1.1,0.9<(1-x)c+xr<2.1, and0<p<0.6.

Abstract: One object of the present invention is to provide a lead-free piezoelectric material excellent in piezoelectric characteristics and superior from the viewpoints of prevention of environmental pollution, protection of environments and ecology. To achieve the object, a piezoelectric ceramic composition is constructed from a piezoelectric ceramic composition within a region in case of being represented by the formula:x[Bi.sub.1/2 Na.sub.1/2 ]TiO.sub.3 -y[MeNbO.sub.3 ]-(z/2)[Bi.sub.2 O.sub.3.Sc.sub.2 O.sub.3 ](wherein Me is K or Na)wherein X, y and z satisfy the following conditions:x+y+z=1, 0<x<1, 0.ltoreq.y<1, 0<z<0.5.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: A semiconductor integrated circuit device includes a pad receiving a power supply potential and a pad receiving a ground potential both formed on a chip, and a power supply potential line and a ground potential line connected to respective pads and formed in a loop manner along a circumference of the chip. The semiconductor integrated circuit device includes a first data output circuit provided for a data output terminal proximate to a predetermined potential pad, and a second data output circuit provided for a data output terminal distant from the predetermined potential pad. First and second data output circuits drive corresponding data output terminals to the predetermined potential in two steps at a lower rate and a higher rate in accordance with an internal output data signal. First and second data output circuits include components for compensating for and canceling an influence on driving the corresponding output nodes due to the difference of distances to the predetermined pad therefrom.

Abstract: A simple instrument for measuring the transmittance of a film impregnated with a pyridylazo-2-naphthol or dimethylphenylazo-2-naphthol dye having a continuous absorption spectrum having a plurality of absorption peaks in the wavelength range of from 350 to 800 nm, which comprises a light-emitting diode having a peak of relative emission intensity in the vicinity of a wavelength of 450 nm; a means for allowing the diode to emit a light and adjusting the quantity of the light; a band-pass filter which consists essentially of a resin film or glass plate coated with a coating composition composed essentially of at least one pigment selected from the group consisting of a Phthalocyanine Blue pigment and an organic violet pigment finely dispersed in a binder resin, and which has a peak of transmittance in the range of from 330 to 480 nm, the transmittance at the peak being 40% or more the transmittances at 260 nm or less and 520 nm or more being 1% or less, said band-pass filter being placed in such a position that

Abstract: A semiconductor integrated circuit device includes a pad receiving a power supply potential and a pad receiving a ground potential both formed on a chip, and a power supply potential line and a ground potential line connected to respective pads and formed in a loop manner along a circumference of the chip. The semiconductor integrated circuit device includes a first data output circuit provided for a data output terminal proximate to a predetermined potential pad, and a second data output circuit provided for a data output terminal distant from the predetermined potential pad. First and second data output circuits drive corresponding data output terminals to the predetermined potential in two steps at a lower rate and a higher rate in accordance with an internal output data signal. First and second data output circuits include components for compensating for and canceling an influence on driving the corresponding output nodes due to the difference of distances to the predetermined pad therefrom.

Abstract: A gas permselective membrane comprising a porous support having fine pores continuous in the thickness direction and a layer of a polymer laminated on the surface of said porous support, said polymer comprising a copolymer of (a) and (b), where (a) represents silarylene-siloxane structural units represented by the following general formula ##STR1## wherein R stands for an alkyl group having 1 to 10 carbon atoms, a phenyl group, a nucleus-substituted phenyl group having 6 to 20 carbon atoms, or a substituted alkyl group having 1 to 10 carbon atoms, Ar stands for ##STR2## and m is a number of from 5 to 8000, and wherein (b) represents diorganosiloxane structural units represented by the following general formula ##STR3## wherein R.sub.1 and R.sub.