Patents by Inventor Masakazu Sagawa

Masakazu Sagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050189866
    Abstract: A flat panel display apparatus includes a rear substrate in which a number of cold cathode devices for emitting electrons are formed on an insulative substrate; a display substrate in which phosphors are arranged in a matrix shape on a translucent substrate; supporting members which are arranged between the rear substrate and the display substrate and maintain intervals between them; and frame members, in which a space surrounded by the rear substrate, the display substrate, and the frame members is set to a vacuum atmosphere. It then becomes possible to provide an apparatus in which there is no remarkable change between a scanning line resistance value in the scanning line direction in a portion with spacers and that in a portion without a spacer, a luminance variation can be reduced, and the apparatus has a conduction connection structure of the spacers and the scanning lines.
    Type: Application
    Filed: January 27, 2005
    Publication date: September 1, 2005
    Applicant: Hitachi Ltd.
    Inventors: Yoshie Kodera, Tetsu Ohishi, Toshimitsu Watanabe, Mutsumi Suzuki, Masakazu Sagawa, Akinori Maeda
  • Publication number: 20050156533
    Abstract: A cold cathode type flat panel display which is an image display device including a vacuum panel container composed of a cathode substrate in which plural cold cathode type electron sources are arranged, an anode substrate, plural spacers for supporting the cathode substrate and the anode substrate, and a glass frame. Plural electrical lines extend in a line direction and a row direction across an interlayer insulator on the cathode substrate. Parts of lines positioned in an upper layer of the plural electrical lines are made into scan lines and lines positioned in a lower layer are made into data lines. Further, parts of the electrical lines positioned in the upper layer are made into ground lines for giving ground voltage to the spacers.
    Type: Application
    Filed: March 11, 2005
    Publication date: July 21, 2005
    Inventors: Masakazu Sagawa, Toshiaki Kusunoki, Mutsumi Suzuki, Nobuaki Kabuto
  • Patent number: 6894334
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: May 17, 2005
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20050094429
    Abstract: A display having hot electron type electron sources displaying an image by a line sequential scanning scheme is provided to prevent poor brightness uniformity along scan lines. The hot electron type electron source is provided with a top electrode bus line serving as a scan line and a bottom electrode bus line serving as a data line. The top electrode bus line has a sheet resistance lower than that of the bottom electrode. The wire sheet resistance of the scam line can be reduced to several m/square. When forming a 40 inch large screen FED using the hot electron type electron sources, a voltage drop amount produced in the scan line can be suppressed below an allowable range. As a result, high quality image without poor brightness uniformity can be obtained.
    Type: Application
    Filed: December 7, 2004
    Publication date: May 5, 2005
    Inventors: Masakazu Sagawa, Mutsumi Suzuki, Toshiaki Kusunoki
  • Publication number: 20050093421
    Abstract: A flat type display device is provided which is capable of accurately and easily assembling a spacer when arranging the spacer while reducing the danger of damaging the metal back. In the display device, a plurality of fine holes each having a fluorescent materials are formed on a light transparency substrate and a metal sheet is arranged by a black oxide film formed on the surface of the light transparency substrate side so as to obtain a light absorbing layer. A plurality of concave portions are provided on a surface of the metal sheet of the rear substrate side. A metal back having an openings corresponding to predetermined areas containing each of the concave portions is superimposed on the metal sheet, thereby constituting an acceleration electrode of two-layer structure. The spacer is inserted into the concave portion on the metal sheet exposed in the opening of the metal back.
    Type: Application
    Filed: August 31, 2004
    Publication date: May 5, 2005
    Inventors: Yoshie Kodera, Masakazu Sagawa, Toshiaki Kusunoki, Tetsu Ohishi, Yuichi Sawai
  • Patent number: 6873115
    Abstract: A display having hot electron type electron sources displaying an image by a line sequential scanning scheme is provided to prevent poor brightness uniformity along scan lines. The hot electron type electron source is provided with a top electrode bus line serving as a scan line and a bottom electrode bus line serving as a data line. The top electrode bus line has a sheet resistance lower than that of the bottom electrode. The wire sheet resistance of the scam line can be reduced to several m/square. When forming a 40 inch large screen FED using the hot electron type electron sources, a voltage drop amount produced in the scan line can be suppressed below an allowable range. As a result, high quality image without poor brightness uniformity can be obtained.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: March 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Sagawa, Mutsumi Suzuki, Toshiaki Kusunoki
  • Patent number: 6873309
    Abstract: A display apparatus includes: a plurality of luminance modulation elements each modulated in luminance by a voltage of a positive polarity applied thereto, each of the luminance modulation elements being not modulated in luminance by a voltage of an opposite polarity applied thereto; a plurality of first lines electrically coupled to first electrodes of the plurality of luminance modulation elements; a plurality of second lines electrically coupled to second electrodes of the plurality of luminance modulation elements, the plurality of second lines intersecting the plurality of first lines; a first drive unit coupled to the plurality of first lines, the first drive unit outputting scanning pulses; and a second driver unit coupled to the plurality of second lines. The first drive unit sets the first lines in a nonselection state to a high impedance state having a higher impedance as compared with the first lines in a selection state.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: March 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Mutsumi Suzuki, Toshiaki Kusunoki, Masakazu Sagawa
  • Patent number: 6841946
    Abstract: An object of the present invention is to obtain excellent images which are free from distortion in a flat display apparatus including electron-emitter elements, phosphors, and spacers. A structure of the present invention is such that the display apparatus comprises a display panel including a first substrate having a plurality of electron-emitter elements, a second substrate having phosphors, and spacers; and driving means employing a line-sequential scanning method; wherein scan pulse output is performed by the driving means, and the driving means performs scanning in such a manner that a scan is performed in the direction of approaching a relevant one of the spacers from far. Thus, the present invention realizes the excellent display images which are free from distortion by largely reducing or eliminating influence of charging of the spacers to be exerted on the images.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Mutsumi Suzuki, Masakazu Sagawa, Toshiaki Kusunoki
  • Patent number: 6818941
    Abstract: As the top electrode material of a thin-film electron emitter, a material having a bandgap wider than that of Si and electrical conductivity is used. In particular, a conductive oxide such as an SnO2 or ITO film and a wide-bandgap semiconductor such as GaN or SiC are employed. The electron energy loss in a top electrode through which hot electrons pass can be reduced so as to enhance the electron emission efficiency. A high emission current can be obtained in the case of the same diode current as a prior art. In addition, in the case of the same emission current density as a prior art, a small driving current is enough. A bus line and driving circuits can be simplified.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: November 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Mutsumi Suzuki, Toshiaki Kusunoki, Masakazu Sagawa, Makoto Okai, Akitoshi Ishizaka
  • Publication number: 20040174114
    Abstract: There is disclosed a flat panel display device capable of reducing charging of phosphors and disposing spacers easily and accurately. The flat panel display device has a rear substrate 1 including an insulating substrate 10 provided with many cold cathode elements 19 for emitting electrons, a display substrate 101 including a light-transmissive substrate 110 disposed to face the rear substrate 1, and phosphors 111 disposed on the light-transmissive substrate for generating light when excited by electron beams from the cold cathode elements 19, and a peripheral frame member 116. A space enclosed by the rear substrate 1, the display substrate 101 and the peripheral frame member 116 is made vacuum tight. Provided on the light-transmissive substrate 110 is a metal sheet 120 perforated with plural fine holes 122 arranged in a matrix configuration and having the phosphors 111 disposed therewithin to form a light-emissive region.
    Type: Application
    Filed: October 10, 2003
    Publication date: September 9, 2004
    Inventors: Tetsu Ohishi, Masakazu Sagawa, Yoshie Kodera, Motoyuki Miyata, Akinori Maeda
  • Publication number: 20040164301
    Abstract: An display apparatus arranged in a matrix having plural luminance modulation elements for modulating or do not modulating luminance depending upon application of a voltage of positive or reverse polarity,
    Type: Application
    Filed: February 9, 2004
    Publication date: August 26, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Mutsumi Suzuki, Masakazu Sagawa, Toshiaki Kusunoki
  • Publication number: 20040166600
    Abstract: A display having a second substrate with a phosphor layer formed on the surface and a first substrate disposed opposing to the first substrate and having electron guns formed thereon, said electron guns having a structure of: first conductive film laminated on the first substrate—insulating film—second conductive film, and said insulating film being one formed by anodizing the first conductive film by using a non-aqueous electrolyte containing an organic solvent such as a compound having an alcoholic hydroxyl group and at least one solute selected from salts of inorganic oxo acids and salts of organic carboxylic acids. According to this device, the quality of the insulating film forming the tunneling insulator of electron guns of the MIM diode structure is improved to prolong the service life of the device.
    Type: Application
    Filed: January 12, 2004
    Publication date: August 26, 2004
    Applicants: Hitachi, Ltd., Mitsubishi Chemical Corporation
    Inventors: Masakazu Sagawa, Makoto Okai, Fumikazu Mizutani, Hiroshi Takaha, Makoto Ue
  • Publication number: 20040155289
    Abstract: A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 12, 2004
    Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
  • Patent number: 6765347
    Abstract: The invention realizes a display device that uses thin film cathodes having no contamination of a top electrode and no damage of an electron acceleration layer due to photo process and having no contact failure of the top electrode of the thin film cathode array due to oxidation or breakage of the bus electrode in the frit glass process that is carried out when a panel is manufactured to bring about the high reliability of the wiring connection of the top electrode. To realize the display device, the invention provides a display device having a substrate comprising a base electrode, a top electrode, and an electron acceleration layer disposed between the base electrode and the top electrode, which substrate is formed of arrayed thin film cathodes that emit electrons from the top electrode side by applying a voltage between the base electrode and the top electrode, and a phosphor screen.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: July 20, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Kusunoki, Masakazu Sagawa, Mutsumi Suzuki
  • Publication number: 20040130260
    Abstract: In a cathode substrate of an FED, spacers lines exclusive for connecting spacers to the ground were necessary besides scan lines and data lines, and a cathode substrate having a three-layer line structure was used in the prior art. The present invention realizes a high-reliable cold cathode type flat panel display which is easily produced and keeps performance that can be obtained by the three-layer line structure, using a cathode substrate having a two-layer line structure.
    Type: Application
    Filed: August 27, 2003
    Publication date: July 8, 2004
    Inventors: Masakazu Sagawa, Toshiaki Kusunoki, Mutsumi Suzuki, Nobuaki Kabuto
  • Publication number: 20040124761
    Abstract: The invention provides a display device using thin film type electron sources having a structure that can be formed in a simple manufacturing process. A lower electrode, a protective insulating layer and an interlayer film are formed on a cathode substrate. An upper bus electrode made from a laminated film of a metal film lower layer and a metal film upper layer is provided further on the interlayer film. A film of an upper electrode of a thin film type electron source for each pixel constituted by an insulating layer serving as an electron accelerating layer on the lower electrode and the upper electrode is formed on two stripe electrodes of the upper bus electrode in that pixel and another upper bus electrode in an adjacent pixel by sputtering. Then, the upper electrode is separated by self-alignment due to a setback portion of the metal film lower layer and an appentice of the metal film upper layer of the corresponding upper bus electrode.
    Type: Application
    Filed: December 1, 2003
    Publication date: July 1, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Toshiaki Kusunoki, Masakazu Sagawa, Mutsumi Suzuki
  • Publication number: 20040104655
    Abstract: The device comprises a first substrate with a plurality of electron emitters arranged in a matrix, a second substrate arranged in opposed relation to the first substrate and having a phosphor pattern formed on the surface thereof nearer to the first substrate for emitting light by receiving the electron beam from the electron emitters and a metal thin film for accelerating the electron beam, and a plurality of spacers arranged between the first and second substrates. The spacers each include first sheet-form support members and second sheet-form support members extending in a direction at right angles to the first sheet-form support members. The first sheet-form support members and the second sheet-form support members are coupled or combined with each other to form spaces with a rectangular section parallel to the first or second substrate.
    Type: Application
    Filed: August 7, 2003
    Publication date: June 3, 2004
    Inventors: Yoshie Kodera, Masakazu Sagawa, Mutsumi Suzuki, Motoyuki Miyata, Toshiaki Kusunoki, Akinori Maeda, Hidenao Kubota
  • Patent number: 6737318
    Abstract: A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: May 18, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
  • Publication number: 20040017160
    Abstract: A display having hot electron type electron sources displaying an image by a line sequential scanning scheme can prevent poor brightness uniformity along scan lines.
    Type: Application
    Filed: January 24, 2003
    Publication date: January 29, 2004
    Inventors: Masakazu Sagawa, Mutsumi Suzuki, Toshiaki Kusunoki
  • Publication number: 20030189255
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Application
    Filed: March 3, 2003
    Publication date: October 9, 2003
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane