Patents by Inventor Masaki Haneda
Masaki Haneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250040284Abstract: A light-receiving device according to an embodiment of the present disclosure includes: a first substrate including a plurality of photoelectric conversion sections that photoelectrically converts light; a second substrate including a plurality of readout circuits that outputs a first signal based on electric charge photoelectrically converted by the photoelectric conversion sections; and a first through-electrode coupled to each of the readout circuits and penetrating the second substrate. The first substrate and the second substrate are stacked by bonding between electrodes to allow a first surface of the first substrate on which an element is formed and a second surface of the second substrate on which an element is formed to be opposed to each other. The first through-electrode is provided for each of the readout circuits or for every plurality of readout circuits.Type: ApplicationFiled: December 7, 2022Publication date: January 30, 2025Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Masaki HANEDA, Hirofumi YAMASHITA, Shoji KOBAYASHI
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Publication number: 20250040285Abstract: An imaging device includes: a first substrate including a pixel region including a plurality of sensor pixels that performs photoelectric conversion; a second substrate stacked on the first substrate and including a plurality of readout circuits, the plurality of readout circuits being each provided for every one or more of the sensor pixels; plurality of first junction electrodes coupled to each of the one or more of the sensor pixels, the plurality of first junction electrodes each having a planar shape having a longitudinal direction in a first direction; and a plurality of second junction electrodes coupled to respective ones of the plurality of readout circuits, and coupled to respective ones of the plurality of first junction electrodes, the plurality of second junction electrodes each having a planar shape having a longitudinal direction in a second direction that ia substantially orthogonal to the first direction.Type: ApplicationFiled: October 18, 2022Publication date: January 30, 2025Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hirofumi YAMASHITA, Masaki HANEDA
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Publication number: 20240381008Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: DAISUKE ITO, KAZUYUKI TOMIDA, MASAKI HANEDA, TSUYOSHI SUZUKI, TAKAAKI MINAMI
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Publication number: 20240304649Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.Type: ApplicationFiled: May 20, 2024Publication date: September 12, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
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Patent number: 12080745Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.Type: GrantFiled: July 25, 2022Date of Patent: September 3, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
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OPTICAL DETECTION DEVICE, MANUFACTURING METHOD OF OPTICAL DETECTION DEVICE, AND ELECTRONIC APPARATUS
Publication number: 20240290813Abstract: An optical detection device including a through electrode is provided. The optical detection device includes a first semiconductor layer having a photoelectric conversion region, a first surface, and a second surface that is a light entrance surface, a second semiconductor layer with a third surface and a fourth surface, a second wiring layer overlapped with the third surface, a third wiring layer overlapped with the fourth surface, a first wiring layer with one surface overlapped with the first surface and another surface overlapped with one of the second wiring layer and the third wiring layer, a first conductor that has a first width, includes a first material, and penetrates the second semiconductor layer in a thickness direction, and a second conductor that has a second width smaller than the first width, includes a second material different from the first material, and penetrates the second semiconductor layer in the thickness direction.Type: ApplicationFiled: June 16, 2022Publication date: August 29, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Masaki HANEDA, Kengo KOTOO, Yoshiki SHIRASU, Kazuki SHIMOMURA, Nobutoshi FUJII, Takaaki HIRANO, Yosuke FUJII, Takashi OINOUE, Suguru SAITO, Toshiyuki ISHIMARU, Keiji OHSHIMA, Shinichi IMAI, Takuya KUROTORI, Tomohiro SUGIYAMA, Ikue MITSUHASHI, Kenichi TOKUOKA -
Publication number: 20240274641Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: ApplicationFiled: March 4, 2024Publication date: August 15, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
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Patent number: 12057462Abstract: Provided is a solid-state imaging device that includes a first substrate which includes a first semiconductor substrate and a first multi-layered wiring layer that are stacked, a second substrate which includes a second semiconductor substrate and a second multi-layered wiring layer that are stacked, and a third substrate which includes a third semiconductor substrate and a third multi-layered wiring layer that are stacked. The solid-state imaging device further includes a first coupling structure for electrically coupling a circuit of the first substrate and a circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or a predetermined wiring line in the third multi-layered wiring layer to each other.Type: GrantFiled: August 9, 2021Date of Patent: August 6, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda
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Patent number: 12052525Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.Type: GrantFiled: June 22, 2020Date of Patent: July 30, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Daisuke Ito, Kazuyuki Tomida, Masaki Haneda, Tsuyoshi Suzuki, Takaaki Minami
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Publication number: 20240243155Abstract: An imaging element according to an embodiment of the present disclosure includes: a wiring layer including a plurality of wiring lines extending in one direction; a first barrier film stacked on the wiring layer and having a first edge surface above any wiring line of the plurality of wiring lines; a first insulating film stacked on the wiring layer and the first barrier film; a first air gap provided between the wiring layer and the first insulating film, and provided between the plurality of wiring lines adjacent to each other; and a second air gap provided above the wiring line above which the first edge surface is provided, the second air gap being provided near the first edge surface.Type: ApplicationFiled: February 22, 2022Publication date: July 18, 2024Inventors: IKUE MITSUHASHI, MASAKI HANEDA
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Patent number: 12027558Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.Type: GrantFiled: August 30, 2021Date of Patent: July 2, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
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Publication number: 20240194718Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.Type: ApplicationFiled: February 20, 2024Publication date: June 13, 2024Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
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Patent number: 12002833Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.Type: GrantFiled: September 27, 2022Date of Patent: June 4, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Patent number: 11990366Abstract: Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.Type: GrantFiled: February 1, 2022Date of Patent: May 21, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Suguru Saito, Nobutoshi Fujii, Masaki Haneda, Kazunori Nagahata
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Patent number: 11955500Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.Type: GrantFiled: February 3, 2022Date of Patent: April 9, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
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Patent number: 11948961Abstract: A solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.Type: GrantFiled: July 20, 2022Date of Patent: April 2, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
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Patent number: 11901392Abstract: There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device that includes a first inter-wiring insulating layer that is provided on a substrate and includes a recess on a side opposite to the substrate, a first wiring layer that is provided inside the recess in the first inter-wiring insulating layer, a sealing film that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer, a second inter-wiring insulating layer that is provided on the first inter-wiring insulating layer to cover the recess, and a gap that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.Type: GrantFiled: October 13, 2022Date of Patent: February 13, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Masaki Haneda
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Publication number: 20230402411Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.Type: ApplicationFiled: August 25, 2023Publication date: December 14, 2023Applicant: SONY GROUP CORPORATIONInventor: Masaki HANEDA
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Patent number: 11804507Abstract: A solid-state imaging device including a first substrate having a pixel unit formed thereon and including a first semiconductor substrate and a first multi-layered wiring layer stacked, a second substrate having a circuit formed thereon and including a second semiconductor substrate and a second multi-layered wiring layer, the circuit having a predetermined function, and a third substrate having a circuit formed thereon and including a third semiconductor substrate and a third multi-layered wiring layer. The first substrate and the second substrate are bonded together such that that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. The solid-state imaging device includes a first coupling structure and a second coupling structure. The first coupling structure electrically couples a circuit of the first substrate and the circuit of the second substrate.Type: GrantFiled: November 23, 2021Date of Patent: October 31, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Ikue Mitsuhashi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Hiroshi Horikoshi, Masaki Haneda
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Patent number: 11776923Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.Type: GrantFiled: February 19, 2021Date of Patent: October 3, 2023Assignee: SONY CORPORATIONInventor: Masaki Haneda