Patents by Inventor Masaki Haneda

Masaki Haneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240381008
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: DAISUKE ITO, KAZUYUKI TOMIDA, MASAKI HANEDA, TSUYOSHI SUZUKI, TAKAAKI MINAMI
  • Publication number: 20240304649
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
  • Patent number: 12080745
    Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 3, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Publication number: 20240290813
    Abstract: An optical detection device including a through electrode is provided. The optical detection device includes a first semiconductor layer having a photoelectric conversion region, a first surface, and a second surface that is a light entrance surface, a second semiconductor layer with a third surface and a fourth surface, a second wiring layer overlapped with the third surface, a third wiring layer overlapped with the fourth surface, a first wiring layer with one surface overlapped with the first surface and another surface overlapped with one of the second wiring layer and the third wiring layer, a first conductor that has a first width, includes a first material, and penetrates the second semiconductor layer in a thickness direction, and a second conductor that has a second width smaller than the first width, includes a second material different from the first material, and penetrates the second semiconductor layer in the thickness direction.
    Type: Application
    Filed: June 16, 2022
    Publication date: August 29, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masaki HANEDA, Kengo KOTOO, Yoshiki SHIRASU, Kazuki SHIMOMURA, Nobutoshi FUJII, Takaaki HIRANO, Yosuke FUJII, Takashi OINOUE, Suguru SAITO, Toshiyuki ISHIMARU, Keiji OHSHIMA, Shinichi IMAI, Takuya KUROTORI, Tomohiro SUGIYAMA, Ikue MITSUHASHI, Kenichi TOKUOKA
  • Publication number: 20240274641
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 15, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
  • Patent number: 12057462
    Abstract: Provided is a solid-state imaging device that includes a first substrate which includes a first semiconductor substrate and a first multi-layered wiring layer that are stacked, a second substrate which includes a second semiconductor substrate and a second multi-layered wiring layer that are stacked, and a third substrate which includes a third semiconductor substrate and a third multi-layered wiring layer that are stacked. The solid-state imaging device further includes a first coupling structure for electrically coupling a circuit of the first substrate and a circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or a predetermined wiring line in the third multi-layered wiring layer to each other.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: August 6, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda
  • Patent number: 12052525
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 30, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Daisuke Ito, Kazuyuki Tomida, Masaki Haneda, Tsuyoshi Suzuki, Takaaki Minami
  • Publication number: 20240243155
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a wiring layer including a plurality of wiring lines extending in one direction; a first barrier film stacked on the wiring layer and having a first edge surface above any wiring line of the plurality of wiring lines; a first insulating film stacked on the wiring layer and the first barrier film; a first air gap provided between the wiring layer and the first insulating film, and provided between the plurality of wiring lines adjacent to each other; and a second air gap provided above the wiring line above which the first edge surface is provided, the second air gap being provided near the first edge surface.
    Type: Application
    Filed: February 22, 2022
    Publication date: July 18, 2024
    Inventors: IKUE MITSUHASHI, MASAKI HANEDA
  • Patent number: 12027558
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 2, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Publication number: 20240194718
    Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
  • Patent number: 12002833
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: June 4, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Patent number: 11990366
    Abstract: Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: May 21, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii, Masaki Haneda, Kazunori Nagahata
  • Patent number: 11955500
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: April 9, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
  • Patent number: 11948961
    Abstract: A solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: April 2, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Patent number: 11901392
    Abstract: There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device that includes a first inter-wiring insulating layer that is provided on a substrate and includes a recess on a side opposite to the substrate, a first wiring layer that is provided inside the recess in the first inter-wiring insulating layer, a sealing film that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer, a second inter-wiring insulating layer that is provided on the first inter-wiring insulating layer to cover the recess, and a gap that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: February 13, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masaki Haneda
  • Publication number: 20230402411
    Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.
    Type: Application
    Filed: August 25, 2023
    Publication date: December 14, 2023
    Applicant: SONY GROUP CORPORATION
    Inventor: Masaki HANEDA
  • Patent number: 11804507
    Abstract: A solid-state imaging device including a first substrate having a pixel unit formed thereon and including a first semiconductor substrate and a first multi-layered wiring layer stacked, a second substrate having a circuit formed thereon and including a second semiconductor substrate and a second multi-layered wiring layer, the circuit having a predetermined function, and a third substrate having a circuit formed thereon and including a third semiconductor substrate and a third multi-layered wiring layer. The first substrate and the second substrate are bonded together such that that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. The solid-state imaging device includes a first coupling structure and a second coupling structure. The first coupling structure electrically couples a circuit of the first substrate and the circuit of the second substrate.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: October 31, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ikue Mitsuhashi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Hiroshi Horikoshi, Masaki Haneda
  • Patent number: 11776923
    Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 3, 2023
    Assignee: SONY CORPORATION
    Inventor: Masaki Haneda
  • Publication number: 20230282666
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a first wiring layer; a first insulating film; and a second insulating film. The first wiring layer includes a plurality of first wiring lines that extends in one direction. The plurality of first wiring lines each has a notch at at least one of ends of one surface in a cross section orthogonal to an extending direction. The first insulating film covers a surface of the first wiring layer. The second insulating film is stacked on the first insulating film. The second insulating film forms a gap between the plurality of adjacent first wiring lines.
    Type: Application
    Filed: July 8, 2021
    Publication date: September 7, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshihisa KAGAWA, Hiroshi HORIKOSHI, Masaki HANEDA, Hiroshi NAKAZAWA, Takatoshi KAMESHIMA
  • Publication number: 20230268369
    Abstract: Provided is a semiconductor device with a wiring layer including a plurality of wiring lines extending in a first direction; a first insulating film stacked on the wiring layer that has a gap region between the plurality of wiring lines adjacent to each other in a second direction; and a second insulating film between the plurality of wiring lines and the first insulating film. Each wiring line includes a metal film and a barrier metal layer. The metal film includes an electrically conductive material including a first metal. The barrier metal layer partially covers surroundings of the metal film in a cross section orthogonal to the first direction and includes a material including a second metal. The second metal prevents diffusion of the first metal. The second insulating film includes an insulating material and covers a portion of the metal film. The insulating material prevents diffusion of the first metal.
    Type: Application
    Filed: July 6, 2021
    Publication date: August 24, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Koichi SEJIMA, Takashi FUKATANI, Kenya NISHIO, Masaki HANEDA, Nobutoshi FUJII, Suguru SAITO