Patents by Inventor Masaki Haneda

Masaki Haneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120181695
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 19, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA
  • Patent number: 8168532
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Limited
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Publication number: 20120052645
    Abstract: A semiconductor device production method includes: forming a gate insulating film on the p-type region of a semiconductor substrate; forming a first aluminum oxide film with an oxygen content lower than stoichiometric composition on the gate insulating film; forming a tantalum-nitrogen-containing film that contains tantalum and nitrogen on the first aluminum oxide film; forming an electrically conductive film on the tantalum-nitrogen-containing film; patterning the electrically conductive film to form a gate electrode; injecting n-type impurities into the p-type region using the gate electrode as a mask; and carrying out heat treatment after the formation of the tantalum-nitrogen-containing film.
    Type: Application
    Filed: April 12, 2011
    Publication date: March 1, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masaki Haneda
  • Publication number: 20120032281
    Abstract: A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow.
    Type: Application
    Filed: April 28, 2011
    Publication date: February 9, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masaki Haneda
  • Patent number: 8067836
    Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaki Haneda, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Michie Sunayama, Takahiro Tabira
  • Patent number: 8003518
    Abstract: A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaki Haneda, Noriyoshi Shimizu, Michie Sunayama
  • Publication number: 20110183515
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Application
    Filed: March 10, 2011
    Publication date: July 28, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
  • Patent number: 7955970
    Abstract: A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
  • Patent number: 7928476
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
  • Patent number: 7803642
    Abstract: A technology for analyzing and evaluating of a change of impurity content distribution at the heat treatment of electrodeposited copper film. There is provided a method of evaluating a semiconductor device, comprising providing an electrodeposited copper film formed while causing the deposition current to transit between the first state of current density and the second state of current density so as to attain a desired impurity content distribution and carrying out analysis and evaluation of any impurity diffusion from a change of impurity content distribution in the electrodeposited copper film between before and after heat treatment.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: September 28, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
  • Publication number: 20100009530
    Abstract: A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer.
    Type: Application
    Filed: September 24, 2009
    Publication date: January 14, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Masaki Haneda, Noriyoshi Shimizu, Michie Sunayama
  • Publication number: 20090321937
    Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.
    Type: Application
    Filed: April 29, 2009
    Publication date: December 31, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masaki HANEDA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Michie SUNAYAMA, Takahiro TABIRA
  • Publication number: 20090317925
    Abstract: A technology for analyzing and evaluating of a change of impurity content distribution at the heat treatment of electrodeposited copper film. There is provided a method of evaluating a semiconductor device, comprising providing an electrodeposited copper film formed while causing the deposition current to transit between the first state of current density and the second state of current density so as to attain a desired impurity content distribution and carrying out analysis and evaluation of any impurity diffusion from a change of impurity content distribution in the electrodeposited copper film between before and after heat treatment.
    Type: Application
    Filed: August 27, 2009
    Publication date: December 24, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
  • Publication number: 20090269925
    Abstract: A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
  • Publication number: 20090146309
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Application
    Filed: November 20, 2008
    Publication date: June 11, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroshi KUDO, Nobuyuki OHTSUKA, Masaki HANEDA, Tamotsu OWADA
  • Publication number: 20090121355
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 14, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA