Patents by Inventor Masaki Narita
Masaki Narita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240100098Abstract: A non-human animal or a part of the same in which the function of Mipep gene is totally or partially lost in adipose tissues or the expression level of Mipep gene in adipose tissues is lowered compared to a wild type; and mesenchymal stem cells or adipocytes in which the function of Mipep gene is totally or partially lost or the expression level of Mipep gene is lowered compared to a wild type. A therapeutic or prophylactic drug that includes the mesenchymal stem cells or adipocytes or a culture supernatant thereof; and a method for preparing a mitokine mixture using the non-human cells, mesenchymal stem cells or adipocytes.Type: ApplicationFiled: February 16, 2022Publication date: March 28, 2024Inventors: Yoshikazu HIGAMI, Masaki KOBAYASHI, Takumi NARITA, Kanari TAKI, Yuto HIRAO
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Patent number: 9346640Abstract: A sheet feeder includes a feeding member to contact a sheet and feed the sheet downstream in a sheet conveyance direction, a friction pad disposed facing the feeding member to contact the feeding member, and a receiving table including a pad mount to hold a side of the friction pad opposite a nip between the friction pad and the feeding member. The friction pad includes a fixed range secured to the pad mount upstream from the nip and a movable range extending downstream the nip in the sheet conveyance direction. A first friction force of the pad mount to act on the movable range of the friction pad is smaller than a second friction force of the sheet to act on the movable range of the friction pad.Type: GrantFiled: March 9, 2015Date of Patent: May 24, 2016Assignee: RICOH COMPANY, LTD.Inventors: Hirofumi Horita, Ikuo Fujii, Mizuna Tanaka, Tomoya Tanaka, Toshikane Nishii, Masaki Narita, Yoshitake Shimizu, Yutaka Aso, Takashi Fujimoto
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Publication number: 20150259164Abstract: A sheet feeder includes a feeding member to contact a sheet and feed the sheet downstream in a sheet conveyance direction, a friction pad disposed facing the feeding member to contact the feeding member, and a receiving table including a pad mount to hold a side of the friction pad opposite a nip between the friction pad and the feeding member. The friction pad includes a fixed range secured to the pad mount upstream from the nip and a movable range extending downstream the nip in the sheet conveyance direction. A first friction force of the pad mount to act on the movable range of the friction pad is smaller than a second friction force of the sheet to act on the movable range of the friction pad.Type: ApplicationFiled: March 9, 2015Publication date: September 17, 2015Applicant: Ricoh Company, Ltd.Inventors: Hirofumi HORITA, Ikuo FUJII, Mizuna TANAKA, Tomoya TANAKA, Toshikane NISHII, Masaki NARITA, Yoshitake SHIMIZU, Yutaka ASO, Takashi FUJIMOTO
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Patent number: 7732338Abstract: A method of fabricating a semiconductor device includes depositing a first film on a workpiece film so that a resist is formed on the first film, processing the first film with the resist serving as a mask, depositing a second film along the first film, processing the second film so that the second film is left only on a sidewall of the first film, depositing a third film on the substrate, exposing a sidewall of the second film, depositing a fourth film along the sidewall and an upper surface of the third film, removing the fourth film except for only its part on the sidewall of the second film, depositing a fifth film on the substrate, planarizing the second to fifth films so that the upper surfaces of the films are exposed, and processing the workpiece film while the second and fifth films serve as a mask.Type: GrantFiled: October 15, 2008Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Masaki Narita
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Publication number: 20090104786Abstract: A method of fabricating a semiconductor device includes depositing a first film on a workpiece film so that a resist is formed on the first film, processing the first film with the resist serving as a mask, depositing a second film along the first film, processing the second film so that the second film is left only on a sidewall of the first film, depositing a third film on the substrate, exposing a sidewall of the second film, depositing a fourth film along the sidewall and an upper surface of the third film, removing the fourth film except for only its part on the sidewall of the second film, depositing a fifth film on the substrate, planarizing the second to fifth films so that the upper surfaces of the films are exposed, and processing the workpiece film while the second and fifth films serve as a mask.Type: ApplicationFiled: October 15, 2008Publication date: April 23, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masaki NARITA
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Patent number: 7208400Abstract: There are provided a gate dielectric film formed on a semiconductor substrate; a gate electrode including: a first electrode layer formed on the gate dielectric film, a dielectric film having a thickness of 5 ? or more and 100 ? or less, and formed on the first electrode layer, and a second electrode layer formed on the dielectric film; and a source and drain regions formed in the semiconductor substrate at both sides of the gate electrode.Type: GrantFiled: October 21, 2003Date of Patent: April 24, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Sasaki, Masaki Narita
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Publication number: 20060137988Abstract: According to an aspect of the present invention, a semiconductor manufacturing apparatus, including: a treatment chamber configured to house a substrate; an electrode which is disposed in said treatment chamber and on which the substrate is placed; a robot arm configured to convey the substrate to said electrode; and a sensor configured to detect a detection pattern of a focus ring which is disposed on an outer peripheral edge portion of said electrode, surrounds an peripheral edge of the substrate placed on said electrode and has the detection pattern, wherein clearance between the substrate and the focus ring is adjusted based on detection result of said sensor, is provided.Type: ApplicationFiled: March 16, 2005Publication date: June 29, 2006Inventors: Katsunori Yahashi, Keiichi Takenaka, Masaki Narita, Itsuko Sakai
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Patent number: 7067761Abstract: A semiconductor device manufacturing system has a vacuum chamber which is provided with a cathode electrode for holding a substrate to be processed and into which a reactive gas for generating discharging plasma by the application of a high-frequency electric power is introduced, a measuring circuit which measures at least one of the impedance of a system including the plasma, the peak-to-peak voltage of a high-frequency signal applied to the plasma, and a self-bias voltage applied to the cathode electrode, and a sense circuit which compares the measured value from the measuring circuit with previously prepared data and senses the change of processing characteristics with time for the substrate in using the discharging plasma or the cleaning time of the inside of the vacuum chamber.Type: GrantFiled: December 23, 2003Date of Patent: June 27, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takanori Matsumoto, Satoshi Shimonishi, Fumio Sato, Masaki Narita
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Publication number: 20060128093Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a mask member on a surface of a semiconductor substrate; and forming a trench in the semiconductor substrate by selectively etching the semiconductor substrate with a mask of the mask member under a certain pressure. The pressure is changed on arrival of (Etching Depth)/(Aperture Width in said surface) at 30 or more for the remainder of the etching by a factor ranging from 1/2 to 9/10 relative to the pressure at the time of the arrival.Type: ApplicationFiled: April 14, 2005Publication date: June 15, 2006Inventors: Keiichi Takenaka, Katsunori Yahashi, Itsuko Sakai, Masaki Narita
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Publication number: 20060057785Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising introducing a work piece comprising a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, and a gate electrode film formed on the gate insulation film, into a chamber, and forming a gate electrode by selectively etching the gate electrode film relative to the gate insulation film by anisotropic dry etching in the chamber, wherein forming the gate electrode includes etching the gate electrode film under a condition that a residence time of an etching gas in the chamber is 100 milliseconds or shorter, at least after a part of the gate insulation film is exposed.Type: ApplicationFiled: November 23, 2004Publication date: March 16, 2006Inventors: Tomoya Satonaka, Toshiyuki Sasaki, Masaki Narita
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Patent number: 6989073Abstract: A semiconductor device manufacturing system has a vacuum chamber which is provided with a cathode electrode for holding a substrate to be processed and into which a reactive gas for generating discharging plasma by the application of a high-frequency electric power is introduced, a measuring circuit which measures at least one of the impedance of a system including the plasma, the peak-to-peak voltage of a high-frequency signal applied to the plasma, and a self-bias voltage applied to the cathode electrode, and a sense circuit which compares the measured value from the measuring circuit with previously prepared data and senses the change of processing characteristics with time for the substrate in using the discharging plasma or the cleaning time of the inside of the vacuum chamber.Type: GrantFiled: December 23, 2003Date of Patent: January 24, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takanori Matsumoto, Satoshi Shimonishi, Fumio Sato, Masaki Narita
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Publication number: 20050215062Abstract: A method of manufacturing a semiconductor device involves etching a film of a metal oxide formed above a semiconductor substrate, by using an etching gas. The etching gas includes a reducing gas which is capable of reducing the metal oxide and is non-reactive with the metal, and a reactive gas which is capable of etching the metal.Type: ApplicationFiled: March 15, 2005Publication date: September 29, 2005Inventors: Osamu Miyagawa, Masaki Narita, Tokuhisa Ohiwa
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Patent number: 6911398Abstract: A method of making a semiconductor device, comprises preparing a plurality of lots each including semiconductor substrates to be processed, the plurality of lots including at least first and second lots, processing the plurality of lots for every one lot, using a semiconductor manufacturing apparatus, judging whether or not the semiconductor manufacturing apparatus is subjected to cleaning before the second lot is processed, depending upon both a first processing type of the first lot to be processed and a second processing type of the second lot to be processed after the first lot, and processing the second lot without the cleaning in the case where the second lot does not require the cleaning.Type: GrantFiled: March 28, 2002Date of Patent: June 28, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Narita, Katsuya Okumura, Tokuhisa Ohiwa
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Patent number: 6887802Abstract: A method of manufacturing a semiconductor device includes forming a first low dielectric constant insulating film over a semiconductor substrate, forming a photoresist pattern on the first low dielectric constant insulating film, etching the first low dielectric constant insulating film to form a concave portion therein, using the photoresist pattern, burying a conductive film in the concave portion after the photoresist pattern is removed, removing an altered layer formed on a sidewall of the concave portion of the first low dielectric constant insulating film after the conductive film is buried, the altered layer being formed when the photoresist pattern is removed, and forming a second low dielectric constant insulating film so as to fill a gap of the sidewall of the concave portion therewith, the gap resulting from removing the altered layer.Type: GrantFiled: June 9, 2003Date of Patent: May 3, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Narita, Koichi Sato, Tokuhisa Ohiwa
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Publication number: 20050023592Abstract: There are provided a gate dielectric film formed on a semiconductor substrate; a gate electrode including: a first electrode layer formed on the gate dielectric film, a dielectric film having a thickness of 5 ? or more and 100 ? or less, and formed on the first electrode layer, and a second electrode layer formed on the dielectric film; and a source and drain regions formed in the semiconductor substrate at both sides of the gate electrode.Type: ApplicationFiled: October 21, 2003Publication date: February 3, 2005Inventors: Toshiyuki Sasaki, Masaki Narita
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Publication number: 20040188739Abstract: A semiconductor device includes a semiconductor substrate, a trench including a narrowed portion and a main part, a diameter of the narrowed portion being coaxially smaller than a diameter of the trench at the main part, a first capacitor electrode provided in the semiconductor substrate so as to surround the trench inclusive of the narrowed portion, a capacitor insulating film provided along a surface of the first capacitor electrode, a second capacitor electrode provided inside the trench.Type: ApplicationFiled: January 8, 2004Publication date: September 30, 2004Inventors: Keiichi Takenaka, Itsuko Sakai, Masaki Narita, Tokuhisa Ohiwa, Atsuo Sanda, Katsunori Yahashi
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Publication number: 20040149698Abstract: A semiconductor device manufacturing system has a vacuum chamber which is provided with a cathode electrode for holding a substrate to be processed and into which a reactive gas for generating discharging plasma by the application of a high-frequency electric power is introduced, a measuring circuit which measures at least one of the impedance of a system including the plasma, the peak-to-peak voltage of a high-frequency signal applied to the plasma, and a self-bias voltage applied to the cathode electrode, and a sense circuit which compares the measured value from the measuring circuit with previously prepared data and senses the change of processing characteristics with time for the substrate in using the discharging plasma or the cleaning time of the inside of the vacuum chamber.Type: ApplicationFiled: December 23, 2003Publication date: August 5, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Takanori Matsumoto, Satoshi Shimonishi, Fumio Sato, Masaki Narita
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Publication number: 20040134609Abstract: A semiconductor device manufacturing system has a vacuum chamber which is provided with a cathode electrode for holding a substrate to be processed and into which a reactive gas for generating discharging plasma by the application of a high-frequency electric power is introduced, a measuring circuit which measures at least one of the impedance of a system including the plasma, the peak-to-peak voltage of a high-frequency signal applied to the plasma, and a self-bias voltage applied to the cathode electrode, and a sense circuit which compares the measured value from the measuring circuit with previously prepared data and senses the change of processing characteristics with time for the substrate in using the discharging plasma or the cleaning time of the inside of the vacuum chamber.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Takanori Matsumoto, Satoshi Shimonishi, Fumio Sato, Masaki Narita
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Publication number: 20040134610Abstract: A semiconductor device manufacturing system has a vacuum chamber which is provided with a cathode electrode for holding a substrate to be processed and into which a reactive gas for generating discharging plasma by the application of a high-frequency electric power is introduced, a measuring circuit which measures at least one of the impedance of a system including the plasma, the peak-to-peak voltage of a high-frequency signal applied to the plasma, and a self-bias voltage applied to the cathode electrode, and a sense circuit which compares the measured value from the measuring circuit with previously prepared data and senses the change of processing characteristics with time for the substrate in using the discharging plasma or the cleaning time of the inside of the vacuum chamber.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Takanori Matsumoto, Satoshi Shimonishi, Fumio Sato, Masaki Narita
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Publication number: 20040137746Abstract: A semiconductor device manufacturing system has a vacuum chamber which is provided with a cathode electrode for holding a substrate to be processed and into which a reactive gas for generating discharging plasma by the application of a high-frequency electric power is introduced, a measuring circuit which measures at least one of the impedance of a system including the plasma, the peak-to-peak voltage of a high-frequency signal applied to the plasma, and a self-bias voltage applied to the cathode electrode, and a sense circuit which compares the measured value from the measuring circuit with previously prepared data and senses the change of processing characteristics with time for the substrate in using the discharging plasma or the cleaning time of the inside of the vacuum chamber.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Takanori Matsumoto, Satoshi Shimonishi, Fumio Sato, Masaki Narita