Abstract: An arithmetic operation unit includes: a first multiplier configured to multiply two first input data to calculate first arithmetic data; a second multiplier configured to multiply two second input data to calculate second arithmetic data; a first adder configured to add the first arithmetic data and the second arithmetic data to calculate third arithmetic data; a first arithmetic selector configured to select one of the first arithmetic data and the third arithmetic data; a second arithmetic selector configured to select one of the second arithmetic data and the third arithmetic data; a second adder configured to add third input data and arithmetic data selected by the first arithmetic selector to calculate first arithmetic result data; and a third adder configured to add input fourth data and arithmetic data selected by the second arithmetic selector to calculate second arithmetic result data.

Abstract: An operation processing apparatus includes: a plurality of operation elements; a plurality of first data storages disposed so as to correspond to the respective operation elements and each configured to store first data; and a shared data storage shared by the plurality of operation elements and configured to store second data, each of the plurality of operation elements are configured to perform an operation using the first data and the second data.

Abstract: An arithmetic operation unit includes: a first multiplier configured to multiply two first input data to calculate first arithmetic data; a second multiplier configured to multiply two second input data to calculate second arithmetic data; a first adder configured to add the first arithmetic data and the second arithmetic data to calculate third arithmetic data; a first arithmetic selector configured to select one of the first arithmetic data and the third arithmetic data; a second arithmetic selector configured to select one of the second arithmetic data and the third arithmetic data; a second adder configured to add third input data and arithmetic data selected by the first arithmetic selector to calculate first arithmetic result data; and a third adder configured to add input fourth data and arithmetic data selected by the second arithmetic selector to calculate second arithmetic result data.

Abstract: An automatic injecting type paste form heat-blowing injection composition comprising a partially crosslinked rubber, an unvulcanized rubber, a crosslinking agent, a plasticizer, a thermoplastic resin, an epoxy resin and a latent curing agent thereof, and a blowing agent. This composition can be used in a injecting and soundproofing method comprising forming an insulation wall by heating and foaming of a injection composition in a closed section of an automobile body part having a closed section frame which is produced by press molding in a body welding step of an automobile manufacturing line, and it has a good anti-stringy property and suffers form less sagging during heating and foaming.

Abstract: A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

Abstract: A control circuit performs control to initialize a plurality of interface circuits connected to a communication circuit and each connected to each of a plurality of communication lines, and detects whether or not initialization of each of the interface circuits has been completed. When the control circuit detects that initialization of all of the interface circuits has been completed, the control circuit controls the communication circuit so as to start data communication via the interface circuits.

Abstract: A data processing system is provided. The data processing system includes a plurality of processors, a cache memory shared by the plurality of processors, in which memory a cache line is divided into a plurality of partial writable regions. The plurality of processors are given exclusive access rights to the partial writable region waits.

Abstract: An error judging circuit includes a first EOR circuit tree that generates a check bit of a correction code by polynomial remainder calculation with respect to a polynomial expression of an original code which is protected from an error with respect to data of m bit block unit by addition in a Galois extension field GF (2m) in SmEC-DmED using Reed-Solomon code, a second EOR circuit tree for generating syndromes from Sn=Y(?n) with respect to code C(x) in which the check bit is added to the original code when a polynomial representation of a code which is to be detected an error and has a possibility that an error is mixed is Y(x), and an error detection circuit unit that detect if there is a one block error, a two block error, or no error based on whether or not an equation of syndromes S12=S0S2 is satisfied.

Abstract: A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in via an external bus, a second buffer unit that retrieves a piece of the data to be written to the cache memory, and a write controlling unit that controls writing of the piece of the data retrieved by the second buffer unit to the cache memory.

Abstract: A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).

Abstract: A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

Abstract: The multi-threading changeover control apparatus of the present invention changes over threads in an information processing device in which a multi-threading method is used, and comprises a thread changeover request unit outputting a thread changeover request signal after a cache miss occurs in which an instruction to be fetched is not stored when the instruction is fetched or a thread execution priority order change request unit outputting a thread execution priority order change request signal.

Abstract: To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data 0 stored in the leftmost position indicates an ID of an entry with the oldest last use time (that is, LRU entry), for example as shown in FIG. 1(1). An LRU control apparatus according to a first embodiment of the present invention refers to the LRU information, and selects an entry corresponding to the storage data 0 (for example, entry 1) from the LRU information as a candidate for the LRU control, based on the storage data 0 as the ID of the entry with the oldest last use time.

Abstract: A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

Abstract: A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.

Abstract: To maintain data consistency in an information processing apparatus in which a nodes are coupled, takeout information indicating that data of the node is taken out to a secondary memory of another node is stored in a directory of each node. When a cache miss occurs during a memory access to a secondary memory of one node, the one node judges whether a destination of the memory access is a main or the secondary memory thereof. If the memory access is destination is the main or secondary memory of the one node, the directory is indexed and retrieved to judge whether a directory hit occurs, and if no directory hit occurs, a memory access is performed by the one node based on the memory access.

Abstract: A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.

Abstract: A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit.

Abstract: Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with respect to a recording position of the MO data is completed. Upon determining that the new registration process is not completed, the second cache cancels the new registration process to ensure that a request of the new registration process is not output to a pipeline.

Abstract: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.