Abstract: A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit.

Abstract: Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with respect to a recording position of the MO data is completed. Upon determining that the new registration process is not completed, the second cache cancels the new registration process to ensure that a request of the new registration process is not output to a pipeline.

Abstract: A cache receives a request from an instruction execution unit, searches for necessary data, outputs the data to the instruction execution unit if there is a cache hit, and instructs a request storage unit to request a move-in of the data if a cache miss occurs. The request storage unit stores therein the request corresponding to the instruction of the cache while the requested process is being executed. A REQID assignment unit reads the request stored in the request storage unit, selects an unused REQID from a REQID table, and assigns the unused REQID to the read request. The REQID is an identification number of the request based on the number of requests set as the maximum number that can be received at a simultaneous time by a system controller of the response side.

Abstract: A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

Abstract: A branch prediction apparatus has a configuration such that a predicted branch target address and an offset are obtained by referring to a branch history, an instruction fetch address and the offset are added to obtain a branch instruction address, the branch instruction address is subtracted from the predicted branch target address to obtain a predicted displacement, and this predicted displacement is compared with a displacement cut-out from an instruction by an instruction decoder, to judge whether the predicted branch target address is correct or not.

Abstract: A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.

Abstract: A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.

Abstract: A memory control device includes a writing unit writing information to a memory module, a reading unit reading the information from the memory module, an error detecting unit executing a detection of an error in the formation in parallel with the reading operation by the reading unit, an error correcting unit correcting the error in the information containing the error detected, and a control unit controlling a transfer and a receipt of the information to and from an external device and stopping, when the error is detected, an output of the information to the external device.

Abstract: A cache memory device in an N-way (N is an integer of 2 or larger) set associative system includes a way detection unit detecting one way exhibiting a specified strength on the basis of a reference history defined as bits representing a win/loss relation between ways and updated so as to indicate one way exhibiting the specified strength, and an error detection unit detecting a bit error in the reference history if the way detection unit does not detect one way exhibiting the specified strength.

Abstract: An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history).

Abstract: The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.

Abstract: The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.

Abstract: In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global registers by the trap, and transmitting data from the master register to the work register for only the global registers if the trap requires transmitting data for the global registers, thereby providing the data processing apparatus performing data transmission to the global registers if the occurring trap requires data for the global registers.

Abstract: An apparatus for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the apparatus includes a data transfer controlling unit that controls the data transfer with the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus, where the input bus transfers data to be input to the computer, and the output bus transfers data output by the computer.

Abstract: A two-pack curable composition of the present invention comprises plastisol liquid A which comppounds a thermoplastic resin and a plasticizer, and liquid B which compounds a gelling agent and is characterized in that it has a sprayable viscosity when liquids A and B are mixed and gels within 30 seconds to 60 minutes after application. This two-pack curable composition can be applied in a body-welding step of an automobile manufacturing line as a body or seam sealer (for water-proofing, air-tightness, dust-proofing or rust-prevention of welded areas), an underbody coating (for anti-chipping), or an adhesive.

Abstract: A cache memory device comprises a secondary tag RAM that partially constitutes a secondary cache memory and employs a set associative scheme having a plurality of ways, and a secondary cache access controller that, when the number of ways in the secondary tag RAM is changed, allocates tags to respective entries so that the total number of entries constituting the secondary tag RAM and the total number of entries after the number of ways is changed are constant.

Abstract: An apparatus for efficient parallel executing instruction avoiding the usage of cross bypasses, the apparatus including an instruction buffer for storing instructions, of decoders for decoding, in parallel, the instructions which simultaneously issue from the instruction buffer, executing units for executing the instructions decoded in the decoders, and an instruction-issuing controlling means for controlling the issuing of the instructions in such a way that, when the instructions are executed, one of the plural executing units executes instructions more frequently than the rest of the plural executing units. The apparatus is preferably incorporated in an information processor to superscalar or out-of-order instruction execution.

Abstract: Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a phantom, and if the entries are not needed, they are erased. If there is an instruction that branches control flow, a phantom entry is intentionally created and instruction pre-fetching is applied to the entry.

Abstract: Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a phantom, and if the entries are not needed, they are erased. If there is an instruction that branches control flow, a phantom entry is intentionally created and instruction pre-fetching is applied to the entry.

Abstract: An automatic injecting type paste form heat-blowing injection composition comprising a partially crosslinked rubber, an unvulcanized rubber, a crosslinking agent, a plasticizer, a thermoplastic resin, an epoxy resin and a latent curing agent thereof, and a blowing agent. This composition can be used in a injecting and soundproofing method comprising forming an insulation wall by heating and foaming of a injection composition in a closed section of an automobile body part having a closed section frame which is produced by press molding in a body welding step of an automobile manufacturing line, and it has a good anti-stringy property and suffers form less sagging during heating and foaming.