Abstract: An apparatus for efficient parallel executing instruction avoiding the usage of cross bypasses, the apparatus including an instruction buffer for storing instructions, of decoders for decoding, in parallel, the instructions which simultaneously issue from the instruction buffer, executing units for executing the instructions decoded in the decoders, and an instruction-issuing controlling means for controlling the issuing of the instructions in such a way that, when the instructions are executed, one of the plural executing units executes instructions more frequently than the rest of the plural executing units. The apparatus is preferably incorporated in an information processor to superscalar or out-of-order instruction execution.

Abstract: A memory control device includes a writing unit writing information to a memory module, a reading unit reading the information from the memory module, an error detecting unit executing a detection of an error in the formation in parallel with the reading operation by the reading unit, an error correcting unit correcting the error in the information containing the error detected, and a control unit controlling a transfer and a receipt of the information to and from an external device and stopping, when the error is detected, an output of the information to the external device.

Abstract: Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a phantom, and if the entries are not needed, they are erased. If there is an instruction that branches control flow, a phantom entry is intentionally created and instruction pre-fetching is applied to the entry.

Abstract: A branch prediction apparatus has a configuration such that a predicted branch target address and an offset are obtained by referring to a branch history, an instruction fetch address and the offset are added to obtain a branch instruction address, the branch instruction address is subtracted from the predicted branch target address to obtain a predicted displacement, and this predicted displacement is compared with a displacement cut-out from an instruction by an instruction decoder, to judge whether the predicted branch target address is correct or not.

Abstract: This is an instruction fetch control device supplying instructions to an instruction execution unit. The device comprises a plurality of instruction buffers storing an instruction string to be supplied to the instruction execution unit and a designation unit designating an instruction buffer storing the instruction string to be supplied next for each of the plurality of instruction buffers.

Abstract: The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.

Abstract: When an instruction stored in a specific instruction buffer is the same as another instruction stored in another instruction buffer and logically subsequent to the instruction in the specific instruction buffer, a connection is made from the instruction buffer storing a logically and immediately preceding instruction, not the instruction in the other instruction buffer, to the specific instruction buffer without the instruction in the other instruction buffer, and a loop is generated by instruction buffers, thereby performing a short loop in an instruction buffer system capable of arbitrarily connecting a plurality of instruction buffers.

Abstract: A branch history memory stores the branch history. The branch history represents the results in the past. When processing of a branch instruction is finished, a branch history update section updates the branch history corresponding to the branch instruction, based on the processing result. A branch history table update section updates the branch history in a branch history table. The branch history stores the number of recent continuous branching successful and the number recent of continuous branching failures.

Abstract: The present invention aims at improving the performance of the process of an information processing apparatus which includes an instruction fetch port, and can detect the possibility for the overwrite of an instruction fetched from the instruction fetch port by correctly detecting the length of an instruction sequence already stored in an instruction buffer for storing an instruction to be fetched before the execution of instructions, and an instruction to be determined in the instructions being or already executed, and by correctly detecting the possibility for the overwrite of the contents of an instruction fetched from one instruction port. The information processing apparatus comprises: an instruction fetch counter unit for counting the length of an instruction sequence containing all instructions which are fetched before the last fetched instruction.

Abstract: A pipeline process system, a super-scalar process system, or an out-of-order-execution process system is applied to an information processing device. A sequence of instructions containing a branch instruction, especially a subroutine, can be processed at a high speed using a branch history and a return address stack storing a return address corresponding to a subroutine call instruction. To successfully perform the process, when an instruction detected as a bit in the branch history is a subroutine return instruction, an address of a branched-to instruction registered in the branch history is compared with all return addresses stored in valid entries in the return address stack. A unit is provided to transmit a matching address as a return address of the return instruction to an instruction fetch unit for fetching an instruction.

Abstract: The present invention provides a coating type reinforcement composition of sheet metal which can be applied under warming for ensuring satisfactory levels of tensile rigidity and resistance to dent of a thin sheet metal mainly due to weight reduction of an automobile body, or for collision safety, and which improve a bending strength and a rigidity of the sheet metal without causing a distortion to the sheet metal.

Abstract: A pipeline process system, a super-scalar process system, or an out-of-order-execution process system is applied to an information processing device. A sequence of instructions containing a branch instruction, especially a subroutine, can be processed at a high speed using a branch history and a return address stack storing a return address corresponding to a subroutine call instruction. To successfully perform the process, when an instruction detected as a bit in the branch history is a subroutine return instruction, an address of a branched-to instruction registered in the branch history is compared with all return addresses stored in valid entries in the return address stack. A unit is provided to transmit a matching address as a return address of the return instruction to an instruction fetch unit for fetching an instruction.

Abstract: If a base register value, an index register value and a displacement value are given in the case of operand access, these values are inputted to an arithmetic unit to generate a correctly calculated logical address. Simultaneously, a logical address predicting unit predicts a logical address. An absolute address is predicted based on the predicted logical address by using an absolute address history table. Access to a cache memory (LBS) based on an absolute address is made using the predicted absolute address to obtain cache data. Then, the arithmetic unit calculates a correct absolute address using the correctly calculated address using a TLB and checks if the correct absolute address coincides with the predicted absolute address so as to perform result confirmation of the cache data read from the LBS. In the case of instruction fetch, similar processing is carried out except that the calculation of a logical address is not performed.

Abstract: In an instruction fetch control unit which issues an instruction fetch request to an instruction cache, an instruction can be prefetched. The instruction fetch control unit includes a fetch address generation unit, a branch history, and a priority determination circuit, and determines whether the priority determination circuit issues an instruction fetch request or an instruction prefetch request. In the instruction prefetch, the computation of a prefetch address is performed by the fetch address generation unit. The priority determination circuit determines the priorities of instructions such as instruction fetch, instruction prefetch, instruction refetch, etc., and transmits each request to the instruction cache. An address is selected and output from among a plurality of input addresses by a selector controlled by the priority determination circuit.