Patents by Inventor Masaki Yamanaka

Masaki Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190371829
    Abstract: In formation of a gate electrode, a metal film forming a gate electrode of TFT is formed on a gate insulating film covering a semiconductor layer having an island shape, the gate electrode is formed on the metal film by dry etching, and the exposed gate electrode is subjected to a plasma treatment using oxygen or nitrogen. This prevents formation of needle-shaped or granular crystal while a reduction in production efficiency is suppressed.
    Type: Application
    Filed: February 28, 2017
    Publication date: December 5, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takao SAITOH, Yohsuke KANZAKI, Masahiko MIWA, Masaki YAMANAKA, Seiji KANEKO
  • Publication number: 20190372032
    Abstract: In a right PI layer inclined area, a photosensitive PI layer covering an underlying PI layer exposed from an inorganic film of a moisture-proof layer, a gate insulating layer, a second insulating layer, and a third insulating layer is formed.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 5, 2019
    Inventors: Seiji KANEKO, Yohsuke KANZAKI, Takao SAITOH, Masahiko MIWA, Masaki YAMANAKA
  • Publication number: 20190362656
    Abstract: A flexible organic EL display device includes a polycrystalline silicon layer in which an extent of alignment of a silicon crystal orientation by electron back scatter diffraction patterns with a 001 plane is greater than or equal to 3.
    Type: Application
    Filed: June 30, 2017
    Publication date: November 28, 2019
    Inventors: Takao SAITOH, Masaki YAMANAKA, Yohsuke KANZAKI, Seiji KANEKO, Masahiko MIWA
  • Publication number: 20190363172
    Abstract: In formation of a gate electrode, a second metal film is formed on a first metal film by adding oxygen or nitrogen in an inert gas atmosphere, the first metal film and the second metal film are patterned and subjected to a plasma treatment using oxygen or nitrogen, to form a third metal film. Thus, a gate electrode is formed. This prevents formation of needle-shaped or granular crystal while a reduction in production efficiency is suppressed.
    Type: Application
    Filed: March 7, 2017
    Publication date: November 28, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takao SAITOH, Yohsuke KANZAKI, Masahiko MIWA, Masaki YAMANAKA, Seiji KANEKO
  • Publication number: 20190363154
    Abstract: A photosensitive PI layer fills a bending region and is formed on a third insulating layer in a display region and a terminal region. An opening is formed in the photosensitive PI layer while exposing a gate electrode extension wiring line. A contact hole is formed in a second insulating layer and the third insulating layer.
    Type: Application
    Filed: August 10, 2017
    Publication date: November 28, 2019
    Inventors: Seiji KANEKO, Yohsuke KANZAKI, Takao SAITOH, Masaki YAMANAKA, Masahiko MIWA
  • Publication number: 20190363152
    Abstract: In a part of a frame region defined around a display region, an insulating film having a slit formed on a front surface of the insulating film to extend in a direction intersecting an edge of the display region is provided, and a frame wiring line connected to a light-emitting element of the display region is provided, on the insulating film, to be bent to stride across the slit.
    Type: Application
    Filed: September 12, 2017
    Publication date: November 28, 2019
    Inventors: Yohsuke KANZAKI, Takao SAITOH, Masahiko MIWA, Masaki YAMANAKA, Seiji KANEKO
  • Publication number: 20190355800
    Abstract: At a bending section of a frame region, an opening portion is formed on at least one layer of inorganic film included in a TFT layer, in which a residual layer of the inorganic film is formed, a flattening film is provided to plug the opening portion, and the frame wiring line is provided on the flattening film.
    Type: Application
    Filed: August 3, 2017
    Publication date: November 21, 2019
    Inventors: Takao SAITOH, Yohsuke KANZAKI, Seiji KANEKO, Masahiko MIWA, Masaki YAMANAKA
  • Publication number: 20190326383
    Abstract: The frame wiring line provided in a frame region includes, at a bending section, a plurality of branch wiring lines being divided into a plurality of branches, wherein the plurality of branch wiring lines are arranged at at least two types of heights relative to a resin substrate.
    Type: Application
    Filed: August 22, 2017
    Publication date: October 24, 2019
    Inventors: Masaki YAMANAKA, Yohsuke KANZAKI, Takao SAITOH, Masahiko MIWA, Seiji KANEKO
  • Publication number: 20160288639
    Abstract: A structure for mounting a diesel oxidation catalyst device to a generator motor includes: a generator motor arranged between an engine and a hydraulic pump; a diesel oxidation catalyst device mounted on an upper part of the generator motor; and a bracket provided between the generator motor and the diesel oxidation catalyst device and adapted to separately arrange the diesel oxidation catalyst device above the generator motor, wherein a boss with screw hole erecting upward is formed on an upper part of a generator motor housing, and a lower part of the bracket is fastened to the boss with screw hole with a bolt.
    Type: Application
    Filed: November 19, 2013
    Publication date: October 6, 2016
    Applicant: KOMATSU LTD.
    Inventors: Yuusuke Kikuchi, Masaki Yamanaka, Takashi Sugiguchi
  • Publication number: 20160273441
    Abstract: A structure for mounting a diesel oxidation catalyst device to a generator motor includes: a generator motor arranged between an engine and a hydraulic pump; a diesel oxidation catalyst device having an approximately cylindrical shape and mounted at an upper part of the generator motor; and a bracket provided between the generator motor and the diesel oxidation catalyst device and adapted to separately arrange the diesel oxidation catalyst device above the generator motor, wherein a cylinder center axis of the diesel oxidation catalyst device is within a width of a generator motor housing in a rotation center axis direction.
    Type: Application
    Filed: November 19, 2013
    Publication date: September 22, 2016
    Applicant: KOMATSU LTD.
    Inventors: Yuusuke Kikuchi, Masaki Yamanaka, Takashi Sugiguchi
  • Patent number: 9119311
    Abstract: An electronic device includes a housing including an opening-portion and an annular-projection provided in the vicinity of the opening-portion from the housing, the annular-projection projecting so as to surround a periphery of the opening-portion, a frame member including a tubular-portion having an outer surface that faces the annular-projection to be fitted with the annular-projection, a top plate exposed from the opening-portion with the tubular-portion fitted with the annular-projection, an extension-portion extending from the outer surface of the tubular-portion, the tubular-portion being expanded toward the annular-projection when a pressing force is applied to a surface of the top plate exposed from the opening-portion with the annular-projection and the tubular-portion fitted with each other, and an O-ring that contacts entire peripheries of the outer surface of the tubular-portion and an inner surface of the annular-projection.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 25, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Masaki Yamanaka, Hiroshi Kubo, Takeshi Komuro, Manabu Hongo, Masahiro Fukuhara, Hiroyuki Takita
  • Patent number: 8816437
    Abstract: Disclosed is a semiconductor device in which an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on the same substrate. The first thin film transistor has a first semiconductor layer (11), and the second thin film transistor has a second semiconductor layer (20), a third semiconductor layer (21), and a fourth semiconductor layer (22). The first semiconductor layer (11), the second semiconductor layer (20), the third semiconductor layer (21) and the fourth semiconductor layer (22) are formed of the same film, and the first and second semiconductor layers (11, 20) respectively have slanted portions (11e, 20e) positioned at respective peripheries, and main portions (11m, 20m) made of portions other than the slanted portions.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 26, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Kazushige Hotta
  • Publication number: 20130146879
    Abstract: Disclosed is a semiconductor device in which an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on the same substrate. The first thin film transistor has a first semiconductor layer (11), and the second thin film transistor has a second semiconductor layer (20), a third semiconductor layer (21), and a fourth semiconductor layer (22). The first semiconductor layer (11), the second semiconductor layer (20), the third semiconductor layer (21) and the fourth semiconductor layer (22) are formed of the same film, and the first and second semiconductor layers (11, 20) respectively have slanted portions (11e, 20e) positioned at respective peripheries, and main portions (11m, 20m) made of portions other than the slanted portions.
    Type: Application
    Filed: June 13, 2011
    Publication date: June 13, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masaki Yamanaka, Kazushige Hotta
  • Patent number: 8460954
    Abstract: A semiconductor device includes a thin film transistor and a thin film diode on a same substrate. A semiconductor layer (109) of the thin film transistor and a semiconductor layer (110) of the thin film diode are crystalline semiconductor layers formed by crystallizing the same non-crystalline semiconductor film. The thickness of the semiconductor layer (110) of the thin film diode is greater than the thickness of the semiconductor layer (109) of the thin film transistor, and the surface of the semiconductor layer (110) of the thin film diode is rougher than the surface of the semiconductor layer (109) of the thin film transistor.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: June 11, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Hiroshi Nakatsuji, Naoki Makita
  • Patent number: 8415678
    Abstract: A semiconductor device of the present invention is a semiconductor device including a thin film transistor and a thin film diode. A semiconductor layer (113) of the thin film transistor and a semiconductor layer (114) of the thin film diode are both crystalline semiconductor layers. The semiconductor layer (113) of the thin film transistor and the semiconductor layer (114) of the thin film diode respectively include portions formed by crystallizing the same amorphous semiconductor film. The thickness of the semiconductor layer (114) of the thin film diode is greater than the thickness of the semiconductor layer (113) of the thin film transistor. The difference between the thickness of the semiconductor layer (113) of the thin film transistor and the thickness of the semiconductor layer (114) of the thin film diode is greater than 25 nm.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: April 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Hiroshi Nakatsuji, Naoki Makita
  • Publication number: 20120068182
    Abstract: A semiconductor device of the present invention is a semiconductor device including a thin film transistor and a thin film diode. A semiconductor layer (113) of the thin film transistor and a semiconductor layer (114) of the thin film diode are both crystalline semiconductor layers. The semiconductor layer (113) of the thin film transistor and the semiconductor layer (114) of the thin film diode respectively include portions formed by crystallizing the same amorphous semiconductor film. The thickness of the semiconductor layer (114) of the thin film diode is greater than the thickness of the semiconductor layer (113) of the thin film transistor. The difference between the thickness of the semiconductor layer (113) of the thin film transistor and the thickness of the semiconductor layer (114) of the thin film diode is greater than 25 nm.
    Type: Application
    Filed: May 20, 2010
    Publication date: March 22, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masaki Yamanaka, Hiroshi Nakatsuji, Naoki Makita
  • Patent number: 8106401
    Abstract: Provided are a display device in which variation in output characteristics of the photodiode is suppressed, and a method for manufacturing the display device. The display device is provided with the active matrix substrate (2) and photodiode (6). First, on a substrate of glass (12), a silicon film (8) and an interlayer insulation film (15) for covering the silicon film (8) are formed in this order. Then, a metal film is formed, and metal lines (10, 11) traversing the silicon film (8) are formed by etching the metal film. Then, p-type impurity ions are implanted by using a mask that has an opening (24a) that exposes a portion that overlaps a region where a p-layer (9a) is to be formed, a part of the opening (24a) being formed with the metal line (10). Furthermore, n-type impurity ions are implanted by using a mask that has an opening (25b) that exposes a portion that overlaps a region where an n-layer (9c) is to be formed, a part of the opening (25a) being formed with the metal line (11).
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: January 31, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Hiromi Katoh, Christopher Brown
  • Publication number: 20110198608
    Abstract: A semiconductor device includes a thin film transistor and a thin film diode on a same substrate. A semiconductor layer (109) of the thin film transistor and a semiconductor layer (110) of the thin film diode are crystalline semiconductor layers formed by crystallizing the same non-crystalline semiconductor film. The thickness of the semiconductor layer (110) of the thin film diode is greater than the thickness of the semiconductor layer (109) of the thin film transistor, and the surface of the semiconductor layer (110) of the thin film diode is rougher than the surface of the semiconductor layer (109) of the thin film transistor.
    Type: Application
    Filed: October 22, 2009
    Publication date: August 18, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masaki Yamanaka, Hiroshi Nakatsuji, Naoki Makita
  • Patent number: 7892991
    Abstract: Provided is an elastic network structure having durability and cushioning properties suitable for furniture, bedding such as a bed, seats for vehicles, seats for shipping, etc., the network structure being lightweight and having excellent chemical resistance, excellent light resistance, soft repellency, and excellent cushioning characteristics in a low temperature environment. The elastic network structure comprises a three-dimensional random loop bonded structure obtained by forming random loops with curling treatment of a continuous linear structure having not less than 300 decitex, and by making each loop mutually contact in a molten state to weld the majority of contacted part, the continuous linear structure mainly including a low density polyethylene resin with a specific gravity of not more than 0.94 g/cm3.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: February 22, 2011
    Assignee: Toyo Boseki Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Yoshihiro Matsui
  • Publication number: 20100140631
    Abstract: Provided are a display device in which variation in output characteristics of the photodiode is suppressed, and a method for manufacturing the display device. The display device is provided with the active matrix substrate (2) and photodiode (6). First, on a substrate of glass (12), a silicon film (8) and an interlayer insulation film (15) for covering the silicon film (8) are formed in this order. Then, a metal film is formed, and metal lines (10, 11) traversing the silicon film (8) are formed by etching the metal film. Then, p-type impurity ions are implanted by using a mask that has an opening (24a) that exposes a portion that overlaps a region where a p-layer (9a) is to be formed, a part of the opening (24a) being formed with the metal line (10). Furthermore, n-type impurity ions are implanted by using a mask that has an opening (25b) that exposes a portion that overlaps a region where an n-layer (9c) is to be formed, a part of the opening (25a) being formed with the metal line (11).
    Type: Application
    Filed: April 17, 2008
    Publication date: June 10, 2010
    Inventors: Masaki Yamanaka, Hiromi Katoh, Christopher Brown