Abstract: An electric potential fixing apparatus of the present invention is an electric potential fixing apparatus that is connected to a connection line (17) between two capacitances, the first capacitance (14) and the second capacitance (15) that is directly connected to the first capacitance, comprises the first high resistance (3), the second high resistance (4) that is connected directly to the first high resistance, a voltage dividing unit that outputs electric potential divided by the first high resistance and the second high resistance to the output terminal, the third capacitance (8) that is connected in parallel to at least either of the first high resistance and the second high resistance, and a voltage supply unit (1) operable to maintain constantly electric potential of the connection line between the two capacitances (14) and (15), holding combined total electric charge quantity of the first capacitance and the second capacitance, and the output terminal of the voltage supply unit is connected to a signa

Abstract: An electrostatic capacitance detection circuit 10 comprises an AC voltage generator 11, an operational amplifier 14 of which non-inverting input terminal is connected to specific potential (a ground in this example), an impedance converter 16, a resistance (R1) 12 connected between the AC voltage generator 11 and an inverting input terminal of the operational amplifier 14, a resistance (R2) 13 connected between the inverting input terminal of the operational amplifier 14 and an output terminal of the impedance converter 16, and an impedance element (a capacitor) 15 connected between an output terminal of the operational amplifier 14 and an input terminal of the impedance converter 16. A capacitor to be detected 17 is connected between the input terminal of the impedance converter 16 and the specific potential.

Abstract: An electrostatic capacitance detection circuit 10 comprises an AC voltage generator 11, an operational amplifier 14 of which non-inverting input terminal is connected to specific potential (a ground in this example), an impedance converter 16, a resistance (R1) 12 connected between the AC voltage generator 11 and an inverting input terminal of the operational amplifier 14, a resistance (R2) 13 connected between the inverting input terminal of the operational amplifier 14 and an output terminal of the impedance converter 16, and an impedance element (a capacitor) 15 connected between an output terminal of the operational amplifier 14 and an input terminal of the impedance converter 16, and a capacitor to be detected 17 is connected between the input terminal of the impedance converter 16 and specific potential. The electrostatic capacitance detection circuit 10 and the capacitor 17 are located adjacently.

Abstract: An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.

Abstract: A second operational amplifier (11) of a core unit (1) shorts an inverting input terminal and an output terminal. A signal line (19) is connected to a non-inverting input terminal. A capacitive sensor (18) is connected to the signal line (19). A first operational amplifier (12) earths the non-inverting input terminal. One end of a first resistance (15) and one end of a second resistance (16) are respectively connected to the inverting input terminal. The other end of the first resistance (15) is connected to an alternate current voltage generator (14). The other end of the second resistance (16) is connected to the output terminal of the first operational amplifier (11). A signal output terminal (21) of the core unit (1) is connected to an inverting amplification device (2). An alternate output terminal (22) of the core unit (1) and an inverting output terminal (42) of the inverting amplification device (2) are connected to an addition device (3).

Abstract: An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.

Abstract: An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.

Abstract: A second operational amplifier (11) of a core unit (1) shorts an inverting input terminal and an output terminal. A signal line (19) is connected to a non-inverting input terminal. A capacitive sensor (18) is connected to the signal line (19). A first operational amplifier (12) earths the non-inverting input terminal. One end of a first resistance (15) and one end of a second resistance (16) are respectively connected to the inverting input terminal. The other end of the first resistance (15) is connected to an alternate current voltage generator (14). The other end of the second resistance (16) is connected to the output terminal of the first operational amplifier (11). A signal output terminal (21) of the core unit (1) is connected to an inverting amplification device (2). An alternate output terminal (22) of the core unit (1) and an inverting output terminal (42) of the inverting amplification device (2) are connected to an addition device (3).