Patents by Inventor Masanao Sato

Masanao Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160336244
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Application
    Filed: July 25, 2016
    Publication date: November 17, 2016
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Publication number: 20160035636
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Application
    Filed: October 6, 2015
    Publication date: February 4, 2016
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Patent number: 9199457
    Abstract: An ink jet recording apparatus records an image on a recording material by ejecting a first ink composition through at least one first liquid ejecting nozzle having an open end. The ink jet recording apparatus also includes a platen having a surface on which the recording medium is placed. The surface is away from the open end at a distance PG satisfying the relationship 0.5 mm<PG<2.5 mm. The first ink composition that has been ejected through the first liquid ejecting nozzle is split into a main droplet having a flying velocity Vm and at least one satellite droplet including a satellite droplet having a flying velocity Vs. The flying velocities Vm and Vs satisfy the relationship Vm?Vs<3 m/s.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 1, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Atsushi Muto, Masanao Sato, Ryoichi Tanaka, Satoshi Kimura
  • Patent number: 9165845
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Publication number: 20150137125
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Application
    Filed: January 5, 2015
    Publication date: May 21, 2015
    Inventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
  • Patent number: 8946705
    Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
  • Patent number: 8939571
    Abstract: An ink jet recording apparatus performs recording by discharging an ink composition onto a recording medium. The apparatus includes an ink jet head including a pressure-generating chamber containing an ink composition and applying a discharge pressure to the ink composition, a discharge port from which the ink composition is discharged, and a communicating path for communicating between the pressure-generating chamber and the discharge port. The ink composition is discharged from the discharge port at a discharge rate of 5 m/sec or more and 15 m/sec or less. The communicating path has a length of 40 ?m or more and 600 ?m or less. The ink composition contains a self-dispersible pigment and an organic solvent having a Hansen solubility parameter of 14 (cal/cm3)1/2 or more and 16 (cal/cm3)1/2 or less.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 27, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Masanao Sato, Satoshi Kimura, Tomoyuki Okuyama
  • Patent number: 8912540
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 16, 2014
    Assignee: Renesas Electronics Corporations
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Publication number: 20140361299
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Publication number: 20140347424
    Abstract: An ink jet recording apparatus records an image on a recording material by ejecting a first ink composition through at least one first liquid ejecting nozzle having an open end. The ink jet recording apparatus also includes a platen having a surface on which the recording medium is placed. The surface is away from the open end at a distance PG satisfying the relationship 0.5 mm<PG<2.5 mm. The first ink composition that has been ejected through the first liquid ejecting nozzle is split into a main droplet having a flying velocity Vm and at least one satellite droplet including a satellite droplet having a flying velocity Vs. The flying velocities Vm and Vs satisfy the relationship Vm?Vs<3 m/s.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Atsushi Muto, Masanao Sato, Ryoichi Tanaka, Satoshi Kimura
  • Publication number: 20140340438
    Abstract: An ink jet recording apparatus performs recording by discharging an ink composition onto a recording medium. The apparatus includes an ink jet head including a pressure-generating chamber containing an ink composition and applying a discharge pressure to the ink composition, a discharge port from which the ink composition is discharged, and a communicating path for communicating between the pressure-generating chamber and the discharge port. The ink composition is discharged from the discharge port at a discharge rate of 5 m/sec or more and 15 m/sec or less. The communicating path has a length of 40 ?m or more and 600 or less. The ink composition contains a self-dispersible pigment and an organic solvent having a Hansen solubility parameter of 14 (cal/cm3)1/2 or more and 16 (cal/cm3)1/2 or less.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 20, 2014
    Applicant: Seiko Epson Corporation
    Inventors: Masanao SATO, Satoshi KIMURA, Tomoyuki OKUYAMA
  • Patent number: 8833885
    Abstract: An ink jet recording apparatus records an image on a recording material by ejecting a first ink composition through at least one first liquid ejecting nozzle having an open end. The ink jet recording apparatus also includes a platen having a surface on which the recording medium is placed. The surface is away from the open end at a distance PG satisfying the relationship 0.5 mm<PG<2.5 mm. The first ink composition that has been ejected through the first liquid ejecting nozzle is split into a main droplet having a flying velocity Vm and at least one satellite droplet including a satellite droplet having a flying velocity Vs. The flying velocities Vm and Vs satisfy the relationship Vm?Vs<3 m/s.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 16, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Atsushi Muto, Masanao Sato, Ryoichi Tanaka, Satoshi Kimura
  • Patent number: 8415199
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: April 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Publication number: 20130050336
    Abstract: An ink jet recording apparatus records an image on a recording material by ejecting a first ink composition through at least one first liquid ejecting nozzle having an open end. The ink jet recording apparatus also includes a platen having a surface on which the recording medium is placed. The surface is away from the open end at a distance PG satisfying the relationship 0.5 mm<PG<2.5 mm. The first ink composition that has been ejected through the first liquid ejecting nozzle is split into a main droplet having a flying velocity Vm and at least one satellite droplet including a satellite droplet having a flying velocity Vs. The flying velocities Vm and Vs satisfy the relationship Vm?Vs<3 m/s.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 28, 2013
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Atsushi Muto, Masanao Sato, Ryoichi Tanaka, Satoshi Kimura
  • Patent number: 8264198
    Abstract: A battery pack, a battery charger, a method for charging a battery pack are provided. The battery pack includes a secondary battery, a switch element for controlling charging and discharging the secondary battery, a controller for controlling the switch element, and a communication unit for performing with a battery charger. During charging, an initial charging is switched to a quick charging when a voltage of the secondary battery reaches a predetermined voltage, and the battery charger judges the battery pack as abnormal when the voltage does not reach the predetermined voltage within a timeout period after the initial charging is started. At least one of the timeout period and the predetermined is stored. At least one of the timeout period and the predetermined voltage to be read out is transmitted through the communication unit to the battery charger.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: September 11, 2012
    Assignee: Sony Corporation
    Inventors: Masanao Sato, Koji Umetsu, Osamu Nagashima
  • Publication number: 20120077310
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 29, 2012
    Inventors: Toshihiko AKIBA, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Patent number: 8101433
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Patent number: 8098053
    Abstract: A charger for a lithium ion secondary battery includes a series circuit of a reverse-current preventive switch, a charging switch and a current-detecting resistor, connected between the battery and the ground a charging control circuit controlling the reverse-current preventive switch and the charging switch, so as to make the battery repeat charging and opening at regular intervals, and so as to detect voltage difference between the specified voltage and the open circuit voltage of the battery during the opening; and a constant-current/constant-voltage control circuit commanding constant-current charging at a first set voltage set relatively high in a range not exceeding the upper limit voltage of the battery, so far as the voltage difference does not exceed a predetermined change-over voltage difference, and commanding constant-voltage charging at a second set voltage, which is lowered from the first set voltage, when the voltage difference becomes smaller than the change-over voltage difference.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: January 17, 2012
    Assignee: Sony Corporation
    Inventor: Masanao Sato
  • Patent number: 8035347
    Abstract: A battery charger for charging a secondary battery using a power supply circuit, includes a discrimination circuit to discriminate a constant-current charging mode and a constant-voltage charging mode, and a controller to which a discrimination signal is supplied. When judged as being the constant-current charging mode, the controller sets the current in the constant-current charging mode by using the control signal. When judged as being the constant-voltage charging mode in accordance with the discrimination signal, the controller sets intermittently the end of charging detection current, and sets an end of charging detection period for judging the constant-current charging mode and the constant-voltage charging mode. When the discrimination signal indicates the constant-voltage charging mode in the end of charging detection period, the controller controls to shift to the end of charging detection mode.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 11, 2011
    Assignee: Sony Corporation
    Inventors: Koji Umetsu, Masanao Sato, Kazumi Sato
  • Patent number: 7965563
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: June 21, 2011
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba