Patents by Inventor Masanobu Shirakawa
Masanobu Shirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230259287Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks each including a plurality of cell units, each of the cell units including a plurality of memory cells; and a memory controller. The memory controller is configured to read second data from a second cell unit in a first block in response to first data being written in a first cell unit in the first block, and reserve refresh processing for the first block when the second data satisfies a condition.Type: ApplicationFiled: September 12, 2022Publication date: August 17, 2023Inventors: Marie TAKADA, Masanobu SHIRAKAWA
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Patent number: 11705204Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: January 26, 2022Date of Patent: July 18, 2023Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Publication number: 20230223090Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.Type: ApplicationFiled: February 27, 2023Publication date: July 13, 2023Applicant: KIOXIA CORPORATIONInventors: Masanobu SHIRAKAWA, Tsukasa TOKUTOMI, Marie TAKADA
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Publication number: 20230223097Abstract: According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.Type: ApplicationFiled: March 9, 2023Publication date: July 13, 2023Applicant: Kioxia CorporationInventors: Marie TAKADA, Masanobu SHIRAKAWA
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Patent number: 11698834Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: GrantFiled: April 12, 2022Date of Patent: July 11, 2023Assignee: KIOXIA CORPORATIONInventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
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Patent number: 11699486Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.Type: GrantFiled: May 6, 2022Date of Patent: July 11, 2023Assignee: KIOXIA CORPORATIONInventors: Tomonori Takahashi, Masanobu Shirakawa, Osamu Torii, Marie Takada
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Publication number: 20230213348Abstract: According to one embodiment, an information processing device includes: a first memory; a first receiver; a first determination section; and a first transmitter. The first memory is configured to store first image data of interior of a vehicle at a first point in time. The first receiver is configured to receive second image data of the interior of the vehicle at a second point of time from the vehicle. The first determination section is configured to determine whether a change has been caused in the interior of the vehicle between the first point in time and the second point in time. The first transmitter is configured to transmit first data based on the determination result.Type: ApplicationFiled: March 6, 2023Publication date: July 6, 2023Applicant: KIOXIA CORPORATIONInventors: Hideki YAMADA, Masanobu SHIRAKAWA, Marie KURONAGA
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Publication number: 20230207016Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Riki SUZUKI, Masanobu SHIRAKAWA, Toshikatsu HIDA
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Patent number: 11682464Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.Type: GrantFiled: March 16, 2022Date of Patent: June 20, 2023Assignee: KIOXIA CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa
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Publication number: 20230187008Abstract: According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.Type: ApplicationFiled: February 3, 2023Publication date: June 15, 2023Applicant: Kioxia CorporationInventors: Naomi TAKEDA, Masanobu SHIRAKAWA
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Publication number: 20230186994Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: KIOXIA CORPORATIONInventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA
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Patent number: 11675535Abstract: According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.Type: GrantFiled: September 9, 2020Date of Patent: June 13, 2023Assignee: Kioxia CorporationInventors: Yuta Aiba, Naomi Takeda, Masanobu Shirakawa
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Patent number: 11657875Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: GrantFiled: June 24, 2022Date of Patent: May 23, 2023Assignee: KIOXIA CORPORATIONInventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
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Patent number: 11636914Abstract: According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.Type: GrantFiled: September 10, 2021Date of Patent: April 25, 2023Assignee: Kioxia CorporationInventors: Marie Takada, Masanobu Shirakawa
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Publication number: 20230117717Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Applicant: KIOXIA CORPORATIONInventors: Marie TAKADA, Masanobu SHIRAKAWA, Tsukasa TOKUTOMI
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Patent number: 11626167Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.Type: GrantFiled: December 22, 2020Date of Patent: April 11, 2023Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Tsukasa Tokutomi, Marie Takada
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Patent number: 11625926Abstract: According to one embodiment, an information processing device includes: a first memory; a first receiver; a first determination section; and a first transmitter. The first memory is configured to store first image data of interior of a vehicle at a first point in time. The first receiver is configured to receive second image data of the interior of the vehicle at a second point of time from the vehicle. The first determination section is configured to determine whether a change has been caused in the interior of the vehicle between the first point in time and the second point in time. The first transmitter is configured to transmit first data based on the determination result.Type: GrantFiled: September 11, 2019Date of Patent: April 11, 2023Assignee: KIOXIA CORPORATIONInventors: Hideki Yamada, Masanobu Shirakawa, Marie Kuronaga
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Patent number: 11626142Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.Type: GrantFiled: October 13, 2021Date of Patent: April 11, 2023Assignee: Kioxia CorporationInventors: Marie Takada, Masanobu Shirakawa, Takuya Futatsuyama
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Patent number: 11615850Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.Type: GrantFiled: December 13, 2021Date of Patent: March 28, 2023Assignee: Kioxia CorporationInventors: Masanobu Shirakawa, Takuya Futatsuyama
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Publication number: 20230087010Abstract: A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.Type: ApplicationFiled: March 15, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Hideki YAMADA, Masanobu SHIRAKAWA, Naomi TAKEDA