Patents by Inventor Masanori Nishiguchi

Masanori Nishiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5536974
    Abstract: A semiconductor device having a high packaging yield is disclosed. A light directed to a light reflection area (20) formed on a packaging substrate (10) is reflected with an accurate angle. A light directed to a second light reflection area (50) formed on a semiconductor chip (40) is also reflected with an accurate angle. A relative inclination between the packaging substrate (10) and the semiconductor chip (40) is measured based on the reflection angles of the reflected lights.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: July 16, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5525835
    Abstract: The semiconductor chip module according to the present invention comprises a semiconductor substrate on which a wiring portion is formed, a semiconductor chip 4 mounted so as to face a circuit side up to the wiring portion, a heat sink 3, 3a, 13 with one end contacted to the central portion of an upper surface of the semiconductor chip 4, 4a; and a cap which has an opening 2a for exposing the other end of the heat sink 3, 3a, 13 to the outside, the cap 2 enclosing all of the semiconductor chips 4, 4a. Accordingly, the heat generated from the semiconductor chips 4, 4a can be dissipated through the heat sink 3, 3a, 13 to the outside. It results in providing a semiconductor chip module without inconvenience for operation with high speed.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: June 11, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5525548
    Abstract: A process of manufacturing a semiconductor chip module by mounting a semiconductor chip on a substrate and contacting the chip with a heat sink. A cap is adhered to the substrate and an adhesive material is embedded in a gap between the heat sink and the chip and into a gap between the inner wall of an opening in the cap and the heat sink. As a result, the heat sink is fixed to the cap and the cap is hermetically sealed.
    Type: Grant
    Filed: September 9, 1994
    Date of Patent: June 11, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5461261
    Abstract: The semiconductor chip is provided with bumps each formed by alternately building up two types of metal materials capable of forming an eutectic alloy, and, therefore, an eutectic alloy reaction takes place at each boundary surface between two layers. The entire bump fully melts in the reaction so that the semiconductor chip may be securely connected on the substrate.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: October 24, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5447750
    Abstract: The heat sink is mounted on a semiconductor chip module sealed hermetically with a cap. The heat sink comprises an absorption means for absorbing the heat generated from a semiconductor chip, being inserted into an opening formed in a cap so as to make contact with a semiconductor chip sealed hermetically within a semiconductor chip module; a heat dissipation means exposed outside the cap for dissipating the heat of the semiconductor chip absorbed by the absorption means; and a contact surface disposed between the absorption means and the heat dissipation means and fixed on the upper surface of the cap, and the contact surface at least being coated with an adhesive material. The heat sink mounted on a semiconductor chip module can stably dissipate the heat produced from a semiconductor chip sealed hermetically within the semiconductor chip module.
    Type: Grant
    Filed: November 4, 1994
    Date of Patent: September 5, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5414370
    Abstract: A burn-in apparatus used in burn-in tests includes a burn-in test chamber for accommodating a plurality of semiconductor devices to be tested. Also, the burn-in apparatus includes measuring means for detecting electric characteristics of temperature sensors built in the respective semiconductor devices to individually measure junction temperatures of the semiconductor chips incorporated in the respective semiconductor devices, and laser beam irradiating means or electric heating members. The laser irradiating means or the heating members are controlled by control means, based on outputs of the measuring means. Thus, the junction temperatures are maintained in a set junction temperature range, and the screening accuracy can be improved.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: May 9, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Hashinaga, Masanori Nishiguchi
  • Patent number: 5406212
    Abstract: A burn-in apparatus for use in burn-in tests includes a burn-in test chamber for accommodating a plurality of semiconductor devices to be tested. The burn-in apparatus further includes measuring means for detecting electric characteristics of temperature sensors built in semiconductor devices to measure junction temperatures of the semiconductor chips built in the semiconductor devices. Based on outputs of the measuring means, control means controls electric power feed amounts to the integrated circuits of the semiconductor chips and/or environmental temperatures in the burn-in test chambers. Thus, the junction temperatures are maintained in a set temperature range, and accuracy of screening tests can be improved.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: April 11, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Hashinaga, Masanori Nishiguchi
  • Patent number: 5403400
    Abstract: The heat sink is mounted on a semiconductor chip module sealed hermetically with a cap. The heat sink comprises an absorption means for absorbing the heat generated from a semiconductor chip, being inserted into an opening formed in a cap so as to make contact with a semiconductor chip sealed hermetically within a semiconductor chip module; a heat dissipation means exposed outside the cap for dissipating the heat of the semiconductor chip absorbed by the absorption means; and a contact surface disposed between the absorption means and the heat dissipation means and fixed on the upper surface of the cap, and the contact surface at least being coated with an adhesive material. The heat sink mounted on a semiconductor chip module can stably dissipate the heat produced from a semiconductor chip sealed hermetically within the semiconductor chip module.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: April 4, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5401099
    Abstract: The present invention relates to a method of measuring junction temperature of a diode junction within a semiconductor device. The method has the steps of measuring current/voltage characteristics for various diodes at room temperature, determining an ideal factor for each diode, changing the temperature of the diodes to a selected temperature, remeasuring current/voltage characteristics for each diode, and comparing the measurements that have been made so as to obtain a temperature coefficients.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: March 28, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideaki Nishizawa, Masanori Nishiguchi, Atsushi Miki, Mitsuaki Fujihira
  • Patent number: 5387815
    Abstract: The semiconductor chip module comprises a substrate on which a wiring portion is formed, a semiconductor chip mounted so as to face a circuit side down to the wiring portion, a heat sink with one end in contact with a side opposite to the circuit side of the semiconductor chip, and a cap enclosing the semiconductor chip and having an opening exposing externally the other end of the heat sink. A metal film is formed at least on the inner wall of the opening and on the surface of the heat sink which is inserted into the cap. An adhesive material is filled between the tip portion of the heat sink and the semiconductor chip, while an adhesive material is filled between the metal films.
    Type: Grant
    Filed: July 6, 1992
    Date of Patent: February 7, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5384000
    Abstract: The three-dimensional shape of the surface of a board (12) is measured, and the parallel degree between the board (12) and a semiconductor chip (10) is adjusted on the basis of the measurement result. A board mounting means (13) and a semiconductor chip holding means (11) are moved close to each other, and the semiconductor chip (10) is mounted on the board (12).
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: January 24, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5359285
    Abstract: A burn-in apparatus for use in burn-in tests includes a burn-in test container for accommodating a plurality of semiconductor device. Also, the burn-in apparatus includes a measuring device for individually measuring junction temperatures of semiconductor chips of the respective semiconductor device by detecting electric characteristics of temperature sensors built in the semiconductor chips, and a temperature adjusting device for controlling amounts of heat radiation and conduction of the semiconductor chips. The temperature adjusting device, such as device for controlling air flow rates of air nozzles of the container, is controlled by control device on the basis of outputs of the measuring device. Thus, the junction temperatures can be kept within a predetermined temperature range to thereby improve the accuracy of screening tests.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: October 25, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Hashinaga, Masanori Nishiguchi
  • Patent number: 5348214
    Abstract: A method of mounting a plurality of semiconductor elements each having bump electrodes on a wiring board by pressing the semiconductor elements to the wiring board while aligning the electrodes and heating the structure. In the mounting method, one or more heat sinks are previously joined to the backs opposite to the surfaces with the bump electrodes formed thereon of the semiconductor elements.
    Type: Grant
    Filed: February 2, 1993
    Date of Patent: September 20, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masanori Nishiguchi, Atsushi Miki
  • Patent number: 5339215
    Abstract: A heat sink mounted on a semiconductor chip module sealed hermetically with a cap. The heat sink includes an absorption portion for absorbing the heat generated by a semiconductor chip. The absorption portion is inserted into an opening formed in a cap to contact a semiconductor chip sealed hermetically within the cap. The heat sink further includes a heat dissipation portion exposed outside the cap for dissipating the heat of the semiconductor chip absorbed by the absorption portion.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: August 16, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5327075
    Abstract: A burn-in apparatus used in burn-in tests includes a burn-in test chamber for accommodating a plurality of semiconductor devices to be tested. Also, the burn-in apparatus includes measuring devices for detecting electric characteristics of temperature sensors built in the respective semiconductor devices to individually measure junction temperatures of the semiconductor chips incorporated in the respective semiconductor devices, and laser beam irradiating mechanisms or electric heating members. The laser irradiating mechanisms or the heating members are controlled by control units, based on outputs of the measuring devices. Thus, the junction temperatures are maintained in a set junction temperature range, and the screening accuracy can be improved.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: July 5, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Hashinaga, Masanori Nishiguchi
  • Patent number: 5324381
    Abstract: The three-dimensional shape of the surface of a board (12) is measured, and the parallel degree between the board (12) and a semiconductor chip (10) is adjusted on the basis of the measurement result. A board mounting means (13) and a semiconductor chip holding means (11) are moved close to each other, and the semiconductor chip (10) is mounted on the board (12).
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: June 28, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5302854
    Abstract: The present invention comprises the steps of electrically connecting at least one pair of bumps on a semiconductor device, bringing the bumps into contact with a surface of the packaging substrate and moving the semiconductor device relative to the packaging substrate while monitoring whether at least one pair of electrode terminals formed on the surface of the packaging substrate are electrically connected to each other, positioning the semiconductor device with respect to the packaging substrate at a position where the electrode terminals whose electrical connection is monitored are electrically connected to each other, and packaging the semiconductor electrode on the packaging substrate.
    Type: Grant
    Filed: October 18, 1991
    Date of Patent: April 12, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masanori Nishiguchi, Atsushi Miki
  • Patent number: 5298460
    Abstract: A substrate for packaging a semiconductor device having a bump thereon according to the present invention is characterized by that the substrate has an electrode terminal to which the bump is to be connected, the electrode terminal has a recess formed thereon to the receive at least a top of the bump, and at least a top of the surface of the electrode terminal is covered by a metal layer having a lower melting point than that of the bump.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: March 29, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masanori Nishiguchi, Atsushi Miki
  • Patent number: 5262355
    Abstract: This invention is directed to a method for packaging a semiconductor flip chip on a substrate by face-down bonding in which coherent light is used to irradiate a bonding head and the substrate, and the light reflected by the bonding head and the substrate form interference patterns. Adjustment of the inclination of the bonding head against the substrate is performed by observation of the interference fringes caused by the interference between the light reflected by the bonding head and the light reflected by the substrate.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: November 16, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masanori Nishiguchi, Atsushi Miki
  • Patent number: 5244142
    Abstract: A method of mounting a plurality of semiconductor elements each having bump electrodes on a wiring board by pressing the semiconductor elements to the wiring board while aligning the electrodes and heating the structure. In the mounting method, one or more heat sinks are previously joined to the backs opposite to the surfaces with the bump electrodes formed thereon of the semiconductor elements.
    Type: Grant
    Filed: November 19, 1991
    Date of Patent: September 14, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masanori Nishiguchi, Atsushi Miki