Abstract: When a failure occurs, the present invention makes it possible to reboot after completing prescribed failure processing for respective control parts. A storage system 10 comprises a controller 100 and a logical volume 23. The controller 100 comprises a processor 140 and a memory 150 that is used by the processor, and uses the processor to realize a plurality of control parts 101, 102, and 103. A block OS 101, which is an example of a first control part, controls a block access request to a disk device 21 (logical volume 23). A file OS 103, which is an example of a second control part, is managed by a hypervisor 102. When a failure has occurred inside the controller, the controller reboots after confirming that prescribed failure processing has been completed for each OS 101, 102, and 103.

Abstract: In a computer system having a storage controller that receives a read request or a write request, a processor is configured to send to an interface device either a read-support indication, which is an indication to execute either all or a portion of read processing for read-data of the read request, or a write-support indication, which is an indication for either all or a portion of write processing for write-data of the write request. Then, the interface device, in accordance with either the read-support indication or the write-support indication, is configured to execute either all or a portion of the read processing for the read-data, or all or a portion of the write processing for the write-data, and to send to a host computer either a first response to the effect that the read processing has been completed, or a second response that the write processing has been completed.

Abstract: In a storage subsystem adopting HDD and PCIe-SSD as storage media, as a method for preventing the complication of having to select a removal method while considering the drive type inserted to the drive slot since the method for removing the HDD differs from the method for removing the PCIe-SSD according to the prior art, the present invention provides an LED for displaying whether it is possible to remove the HDD or the PCIe-SSD inserted to the slot of a drive enclosure, wherein when an HDD is inserted in the drive slot, the LED displays that removal of the HDD is enabled when power supply to the HDD is stopped, and when PCIe-SSD is inserted to the drive slot, the LED displays that removal of the SSD is enabled when Downstream Port Containment (DPC) is triggered in the downstream port of the PCIe switch to which the SSD is connected.

Abstract: A storage apparatus comprises a storage unit configured to store data which is read/written by the host apparatus, a compression/expansion unit configured to compress the data using a predetermined algorithm to generate compressed data, and expand the compressed data, and a control unit configured to control writing of data to the storage unit, wherein the control unit is configured to manage, as compression block units, divided compressed data which is obtained by dividing compressed data compressed by the compression/expansion unit into predetermined units, and padding data.

Abstract: An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device.

Abstract: The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor receives a write request from a host computer and data D1 to D3 exist in a cache slot, the microprocessor reads the LBA of each piece of the data, manages each piece of the data D1 to D3 using a bitmap table by associating them with their LBAs, generates a specific command CMD based on the LBAs of the data D1 to D3, adds the data D1 to D3 and addresses ADD1 to ADD3 indicating where the data D1 to D3 are to be stored, to the specific command CMD, and sends it to an FMPK. The FMPK stores each piece of update data in a specified block in the flash memory based on the specific command CMD.

Abstract: An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.

Abstract: A printer apparatus in the present invention includes a feeding mechanism having a feed roller provided at substantially the same height as an upper face of a medium support means and a plurality of roller assemblies having a pinch roller disposed above the feed roller and a printing medium placed on the medium support means is pinched between the feed roller and the pinch roller to be fed in the front and rear direction. The roller assembly is structured of an assembly main body and a roller member which includes the pinch roller and is attachable/detachable with respect to the assembly main body, and a clamp state can be changed by exchanging the roller member depending on material and/or thickness of the printing medium.

Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

Abstract: An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.

Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

Abstract: It is provided a storage system, comprising a storage device for storing data and at least one controller for controlling reading/writing of the data from/to the storage device. The at least one controller each includes a first cache memory for temporarily storing the data read from the storage device by file access, and a second cache memory for temporarily storing the data to be read/written from/to the storage device by block access. The processor reads the requested data from the storage device in the case where data requested by a file read request received from a host computer is not stored in the first cache memory, stores the data read from the storage device in the first cache memory without storing the data in the second cache memory, and transfers the data stored in the first cache memory to the host computer that has issued the file read request.

Abstract: A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprises an inter-memory data transfer control unit including an operation start trigger receiving unit, a parameter acquiring unit, a read unit, and a write unit. When the write unit detects switching of a write destination memory, the write unit confirms write completion as to the memory by a procedure different from writing. When a data transfer instructed by the processor is completed, the write unit confirms write completion as to the write destination memory at the end of the data transfer by the procedure different from writing. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion.

Abstract: According to a prior art storage subsystem, shared memories are mirrored in main memories of two processors providing redundancy. When the consistency of writing order of data is not ensured among mirrored shared memories, the processors must read only one of the mirrored shared memories to have the write order of the read data correspond among the two processors. As a result, upon reading data from the shared memories, it is necessary for a processor to read data from the main memory of the other processor, so that the overhead is increased compared to the case where the respective processors read their respective main memories. According to the storage subsystem of the present invention, a packet redirector having applied a non-transparent bridge enables to adopt a PCI Express multicast to the writing of data from the processor to the main memory, so that the order of writing data into the shared memories can be made consistent among the mirrored memories.

Abstract: According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.

Abstract: An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device.

Abstract: For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state.

Abstract: The processing load when rewriting portions of compressed data is alleviated. A storage apparatus comprises a storage unit which stores data which is read/written by the host apparatus, a compression/expansion unit which compresses the data using a predetermined algorithm to generate compressed data, and expands the compressed data, and a control unit which controls writing of data to the storage unit, wherein the control unit manages, as compression block units, divided compressed data which is obtained by dividing compressed data compressed by the compression/expansion unit into predetermined units, and padding data.

Abstract: A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory.

Abstract: According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.