Abstract: An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.

Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

Abstract: It is provided a storage system, comprising a storage device for storing data and at least one controller for controlling reading/writing of the data from/to the storage device. The at least one controller each includes a first cache memory for temporarily storing the data read from the storage device by file access, and a second cache memory for temporarily storing the data to be read/written from/to the storage device by block access. The processor reads the requested data from the storage device in the case where data requested by a file read request received from a host computer is not stored in the first cache memory, stores the data read from the storage device in the first cache memory without storing the data in the second cache memory, and transfers the data stored in the first cache memory to the host computer that has issued the file read request.

Abstract: A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprises an inter-memory data transfer control unit including an operation start trigger receiving unit, a parameter acquiring unit, a read unit, and a write unit. When the write unit detects switching of a write destination memory, the write unit confirms write completion as to the memory by a procedure different from writing. When a data transfer instructed by the processor is completed, the write unit confirms write completion as to the write destination memory at the end of the data transfer by the procedure different from writing. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion.

Abstract: According to a prior art storage subsystem, shared memories are mirrored in main memories of two processors providing redundancy. When the consistency of writing order of data is not ensured among mirrored shared memories, the processors must read only one of the mirrored shared memories to have the write order of the read data correspond among the two processors. As a result, upon reading data from the shared memories, it is necessary for a processor to read data from the main memory of the other processor, so that the overhead is increased compared to the case where the respective processors read their respective main memories. According to the storage subsystem of the present invention, a packet redirector having applied a non-transparent bridge enables to adopt a PCI Express multicast to the writing of data from the processor to the main memory, so that the order of writing data into the shared memories can be made consistent among the mirrored memories.

Abstract: According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.

Abstract: An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device.

Abstract: For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state.

Abstract: The processing load when rewriting portions of compressed data is alleviated. A storage apparatus comprises a storage unit which stores data which is read/written by the host apparatus, a compression/expansion unit which compresses the data using a predetermined algorithm to generate compressed data, and expands the compressed data, and a control unit which controls writing of data to the storage unit, wherein the control unit manages, as compression block units, divided compressed data which is obtained by dividing compressed data compressed by the compression/expansion unit into predetermined units, and padding data.

Abstract: A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory.

Abstract: According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.

Abstract: The invention relates to a storage device in which MR-IOV is applied to the internal network of a storage controller, whereby the size of the storage device can be easily expanded. The storage device is expanded on the basis of a network having processor-connected RPs, FE I/F, BE I/F, and CM I/F that are connected with a switch. In the switch, a plurality of ports other than those connected to the RPs, FE I/F, BE I/F, and CM I/F are connected with a cross-link. Each processor is allowed to control the FE I/F, BE I/F, or CM I/F either via a path that passes through the cross-link or via a path that does not pass through the cross-link within the unit device. When unit devices are connected to expand the size of a storage device, the cross-link is removed first and then the unit devices are connected with a new cross-link (see FIG. 4).

Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

Abstract: According to a prior art storage subsystem, shared memories are mirrored in main memories of two processors providing redundancy. When the consistency of writing order of data is not ensured among mirrored shared memories, the processors must read only one of the mirrored shared memories to have the write order of the read data correspond among the two processors. As a result, upon reading data from the shared memories, it is necessary for a processor to read data from the main memory of the other processor, so that the overhead is increased compared to the case where the respective processors read their respective main memories. According to the storage subsystem of the present invention, a packet redirector having applied a non-transparent bridge enables to adopt a PCI Express multicast to the writing of data from the processor to the main memory, so that the order of writing data into the shared memories can be made consistent among the mirrored memories.

Abstract: Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet.

Abstract: Memory module groups are provided which include a memory module, which includes memory chips. In the case in which an error chip that is a memory chip that is provided with an error is in a first memory module, a first memory module group that is provided with the error chip is not managed as a memory module group that cannot be used even if an error of the first data element is mis-corrected based on the error detecting code of the first kind. In the case in which an error chip is in a second memory module, a second memory module group that is provided with the error chip is not managed as a memory module group that cannot be used in such a manner that an error of the second data element is not mis-corrected based on the error detecting code of the second kind.

Abstract: Proposed are a storage apparatus and a power consumption estimation method capable of easily and accurately estimating the power consumption of a physical drive without having to use a wattmeter. Operational information concerning a seek amount and a data transfer amount in the relevant hard disk drive which are internally recorded and retained by the respective hard disk drives is collected from each of the hard disk drives, and power consumption of each of the hard disk drives is estimated based on the acquired operational information of each of the hard disk drives.

Abstract: The object of the present invention is to provide a technique in which, in a storage apparatus using a PCI Express switch in an internal network, an EP can be shared among processors even if the EP is incompatible with the MR-IOV. A storage apparatus according to the present invention is provided with a first interface device which controls data input/output to and from a higher-level apparatus, and the first interface device is further provided with multiple virtual function units which provide virtual ports. The first interface device enables any of the virtual function units and does not enable any of the other virtual function units (see FIG. 14).

Abstract: Power consumption is calculated in accordance with an operation state of disk devices without using a power meter in a storage system. The power consumption in accordance with the operation state is calculated as follows. That is, information on the power consumption for every type of hard disks is stored in advance when types of I/O process (random/sequential of read and write) operate at idle time up to a limit state in every type of hard disks. A control unit of the storage system aggregates time waiting a response from the hard disks in every type of I/O process. The power consumption of the disks is calculated on the basis of the information on the power consumption stored in advance and a sum of the waiting time of the response from the hard disks.

Abstract: The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor 112 receives a write request from a host computer 300 and data D1 to D3 exist in a cache slot 117, the microprocessor 112 reads the LBA of each piece of the data, manages each piece of the data D1 to D3 using a bitmap table 118 by associating them with their LBAs, generates a specific command CMD based on the LBAs of the data D1 to D3, adds the data D1 to D3 and addresses ADD1 to ADD3 indicating where the data D1 to D3 are to be stored, to the specific command CMD, and sends it to an FMPK 30. The FMPK 130 stores each piece of update data in a specified block in the flash memory 135 based on the specific command CMD.