Abstract: The invention relates to a storage device in which MR-IOV is applied to the internal network of a storage controller, whereby the size of the storage device can be easily expanded. The storage device is expanded on the basis of a network having processor-connected RPs, FE I/F, BE I/F, and CM I/F that are connected with a switch. In the switch, a plurality of ports other than those connected to the RPs, FE I/F, BE I/F, and CM I/F are connected with a cross-link. Each processor is allowed to control the FE I/F, BE I/F, or CM I/F either via a path that passes through the cross-link or via a path that does not pass through the cross-link within the unit device. When unit devices are connected to expand the size of a storage device, the cross-link is removed first and then the unit devices are connected with a new cross-link (see FIG. 4).

Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

Abstract: According to a prior art storage subsystem, shared memories are mirrored in main memories of two processors providing redundancy. When the consistency of writing order of data is not ensured among mirrored shared memories, the processors must read only one of the mirrored shared memories to have the write order of the read data correspond among the two processors. As a result, upon reading data from the shared memories, it is necessary for a processor to read data from the main memory of the other processor, so that the overhead is increased compared to the case where the respective processors read their respective main memories. According to the storage subsystem of the present invention, a packet redirector having applied a non-transparent bridge enables to adopt a PCI Express multicast to the writing of data from the processor to the main memory, so that the order of writing data into the shared memories can be made consistent among the mirrored memories.

Abstract: Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet.

Abstract: Memory module groups are provided which include a memory module, which includes memory chips. In the case in which an error chip that is a memory chip that is provided with an error is in a first memory module, a first memory module group that is provided with the error chip is not managed as a memory module group that cannot be used even if an error of the first data element is mis-corrected based on the error detecting code of the first kind. In the case in which an error chip is in a second memory module, a second memory module group that is provided with the error chip is not managed as a memory module group that cannot be used in such a manner that an error of the second data element is not mis-corrected based on the error detecting code of the second kind.

Abstract: Proposed are a storage apparatus and a power consumption estimation method capable of easily and accurately estimating the power consumption of a physical drive without having to use a wattmeter. Operational information concerning a seek amount and a data transfer amount in the relevant hard disk drive which are internally recorded and retained by the respective hard disk drives is collected from each of the hard disk drives, and power consumption of each of the hard disk drives is estimated based on the acquired operational information of each of the hard disk drives.

Abstract: The object of the present invention is to provide a technique in which, in a storage apparatus using a PCI Express switch in an internal network, an EP can be shared among processors even if the EP is incompatible with the MR-IOV. A storage apparatus according to the present invention is provided with a first interface device which controls data input/output to and from a higher-level apparatus, and the first interface device is further provided with multiple virtual function units which provide virtual ports. The first interface device enables any of the virtual function units and does not enable any of the other virtual function units (see FIG. 14).

Abstract: Power consumption is calculated in accordance with an operation state of disk devices without using a power meter in a storage system. The power consumption in accordance with the operation state is calculated as follows. That is, information on the power consumption for every type of hard disks is stored in advance when types of I/O process (random/sequential of read and write) operate at idle time up to a limit state in every type of hard disks. A control unit of the storage system aggregates time waiting a response from the hard disks in every type of I/O process. The power consumption of the disks is calculated on the basis of the information on the power consumption stored in advance and a sum of the waiting time of the response from the hard disks.

Abstract: The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor 112 receives a write request from a host computer 300 and data D1 to D3 exist in a cache slot 117, the microprocessor 112 reads the LBA of each piece of the data, manages each piece of the data D1 to D3 using a bitmap table 118 by associating them with their LBAs, generates a specific command CMD based on the LBAs of the data D1 to D3, adds the data D1 to D3 and addresses ADD1 to ADD3 indicating where the data D1 to D3 are to be stored, to the specific command CMD, and sends it to an FMPK 30. The FMPK 130 stores each piece of update data in a specified block in the flash memory 135 based on the specific command CMD.

Abstract: Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet.

Abstract: For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state.

Abstract: The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained.

Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.

Abstract: A storage system of an embodiment of this invention comprises a first transfer engine, a second transfer engine, a first storage device, a second storage device, a processor, and a transfer sequencer which is a device different from the processor. The processor creates transfer sequence information for indicating a sequence of transfers of user data. The transfer sequencer receives the transfer sequence information made by the processor and controls the first and the second transfer engines in accordance with the transfer sequence information. The first and the second transfer engines transfer user data between storage devices in accordance with instructions from the transfer sequencer.

Abstract: For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state.

Abstract: In order to calculate the power of logically-partitioned areas without using a power meter in a storage system logically partitioning a storage area, there is provided a power estimating method in a computer system including a management computer and a storage system connected to the management computer and a host computer. The storage system prepares logical storage-volumes in a real area of plural disk drives. The power estimating method includes the steps of: allowing a third processor to calculate operation rates of the disk drives for access to the logical storage-volumes from operating times of the disk drives for access to the logical storage-volumes; and allowing the third processor to calculate power consumption increments of the disk drives for access to the logical storage-volumes by access types from incremental power consumption information and the calculated operation rates of the disk drives.

Abstract: This invention, in the interface coupled to the server, the disk interface coupled to the second memory to store final data, the cache to store data temporarily, and in the storage system with the MP which controls them, specifies the area by referring to the stored data, and makes the virtual memory area resident in the cache by using the storage system where the specified area is made resident in the cache.

Abstract: In a storage system including a host computer, and a disk control device connected to the host computer for communications therewith, and performs control over a disk device that stores therein data requested for writing from the host computer, for data transmission from a host interface section or a disk interface section to a memory section, when the data asked by a transmission source for storage is stored in a transmission destination, the transmission destination is put in a first mode for communications of forwarding a response back to the transmission source. With such a configuration, favorably provided is the storage system that offers a guarantee of reliability with the improved processing capabilities thereof.

Abstract: Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.