Patents by Inventor Masanori Takada

Masanori Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120324162
    Abstract: For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state.
    Type: Application
    Filed: August 14, 2012
    Publication date: December 20, 2012
    Inventors: Takayuki FUKATANI, Yasutomo YAMAMOTO, Tomohiro KAWAGUCHI, Masanori TAKADA, Yoshiaki EGUCHI
  • Patent number: 8332586
    Abstract: The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: December 11, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Publication number: 20120297244
    Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 22, 2012
    Applicant: HITACHI, LTD.
    Inventors: Jun KITAHARA, Masanori TAKADA, Sadahiro SUGIMOTO
  • Patent number: 8312314
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Patent number: 8266342
    Abstract: A storage system of an embodiment of this invention comprises a first transfer engine, a second transfer engine, a first storage device, a second storage device, a processor, and a transfer sequencer which is a device different from the processor. The processor creates transfer sequence information for indicating a sequence of transfers of user data. The transfer sequencer receives the transfer sequence information made by the processor and controls the first and the second transfer engines in accordance with the transfer sequence information. The first and the second transfer engines transfer user data between storage devices in accordance with instructions from the transfer sequencer.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 11, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Hiroshi Hirayama, Akira Yamamoto
  • Patent number: 8261036
    Abstract: For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: September 4, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Fukatani, Yasutomo Yamamoto, Tomohiro Kawaguchi, Masanori Takada, Yoshiaki Eguchi
  • Patent number: 8250390
    Abstract: In order to calculate the power of logically-partitioned areas without using a power meter in a storage system logically partitioning a storage area, there is provided a power estimating method in a computer system including a management computer and a storage system connected to the management computer and a host computer. The storage system prepares logical storage-volumes in a real area of plural disk drives. The power estimating method includes the steps of: allowing a third processor to calculate operation rates of the disk drives for access to the logical storage-volumes from operating times of the disk drives for access to the logical storage-volumes; and allowing the third processor to calculate power consumption increments of the disk drives for access to the logical storage-volumes by access types from incremental power consumption information and the calculated operation rates of the disk drives.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: August 21, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura
  • Patent number: 8244955
    Abstract: This invention, in the interface coupled to the server, the disk interface coupled to the second memory to store final data, the cache to store data temporarily, and in the storage system with the MP which controls them, specifies the area by referring to the stored data, and makes the virtual memory area resident in the cache by using the storage system where the specified area is made resident in the cache.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: August 14, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Masanori Takada
  • Patent number: 8219747
    Abstract: In a storage system including a host computer, and a disk control device connected to the host computer for communications therewith, and performs control over a disk device that stores therein data requested for writing from the host computer, for data transmission from a host interface section or a disk interface section to a memory section, when the data asked by a transmission source for storage is stored in a transmission destination, the transmission destination is put in a first mode for communications of forwarding a response back to the transmission source. With such a configuration, favorably provided is the storage system that offers a guarantee of reliability with the improved processing capabilities thereof.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: July 10, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Makio Mizuno, Shuji Nakamura, Masanori Takada
  • Patent number: 8219760
    Abstract: Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: July 10, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Fukuda, Nobuyuki Minowa, Naoki Moritoki, Masanori Takada, Masato Shimizu
  • Publication number: 20120169804
    Abstract: To provide a printer apparatus which is capable of suitably clamping a printing medium of various types of material/thickness, for example, a sheet-like medium and a plate-like medium with a simple structure and is capable of feeding the printing medium accurately. A printer apparatus in the present invention includes a feeding mechanism having a feed roller provided at substantially the same height as an upper face of a medium support means and a plurality of roller assemblies having a pinch roller disposed above the feed roller and a printing medium placed on the medium support means is pinched between the feed roller and the pinch roller to be fed in the front and rear direction. The roller assembly is structured of an assembly main body and a roller member which includes the pinch roller and is attachable/detachable with respect to the assembly main body, and a clamp state can be changed by exchanging the roller member depending on material and/or thickness of the printing medium.
    Type: Application
    Filed: September 8, 2010
    Publication date: July 5, 2012
    Applicant: MIMAKI ENGINEERING CO., LTD.
    Inventors: Eiji Miyashita, Masanori Takada
  • Publication number: 20120144252
    Abstract: A first memory area and a second memory area are provided. The first (second) memory area is provided with at least one first (second) memory module group, each of the first (second) memory module group is provided with at least one first (second) memory module, and each of the first (second) memory module is provided with a plurality of memory chip. In the case in which an error chip that is a memory chip that is provided with an error is in the first memory module, a first memory module group that is provided with the error chip is not managed as a memory module group that cannot be used even if there is a possibility that an error of the first data element is mis-corrected based on the error detecting code of the first kind.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 7, 2012
    Inventor: Masanori Takada
  • Publication number: 20120096192
    Abstract: The object of the present invention is to provide a technique in which, in a storage apparatus using a PCI Express switch in an internal network, an EP can be shared among processors even if the EP is incompatible with the MR-IOV. A storage apparatus according to the present invention is provided with a first interface device which controls data input/output to and from a higher-level apparatus, and the first interface device is further provided with multiple virtual function units which provide virtual ports. The first interface device enables any of the virtual function units and does not enable any of the other virtual function units (see FIG. 14).
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Applicant: HITACHI, LTD.
    Inventors: Katsuya Tanaka, Masanori Takada
  • Publication number: 20120059966
    Abstract: The invention relates to a storage device in which MR-IOV is applied to the internal network of a storage controller, whereby the size of the storage device can be easily expanded. The storage device is expanded on the basis of a network having processor-connected RPs, FE I/F, BE I/F, and CM I/F that are connected with a switch. In the switch, a plurality of ports other than those connected to the RPs, FE I/F, BE I/F, and CM I/F are connected with a cross-link. Each processor is allowed to control the FE I/F, BE I/F, or CM I/F either via a path that passes through the cross-link or via a path that does not pass through the cross-link within the unit device. When unit devices are connected to expand the size of a storage device, the cross-link is removed first and then the unit devices are connected with a new cross-link (see FIG. 4).
    Type: Application
    Filed: April 23, 2010
    Publication date: March 8, 2012
    Inventors: Katsuya Tanaka, Masanori Takada
  • Patent number: 8109601
    Abstract: A printer including a medium supporting member that supports a print medium in a state placed thereon, a print head that has nozzles for ejecting ink droplets downward and freely reciprocates above the medium supporting member, and a maintenance device. The maintenance device is disposed to face the lower surface of the print head when the print head is in a standby position and receives residual ink in the nozzles which is ejected from the nozzles when the print head is in the standby position. The maintenance device has an ink receiving chamber that opens upward for receiving the residual ink ejected from the nozzles and a liquid injection member that injects liquid into the ink receiving chamber when the print head is away from a position where the print head faces the ink receiving chamber in the vertical direction.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: February 7, 2012
    Assignee: Mimaki Engineering Co., Ltd.
    Inventor: Masanori Takada
  • Publication number: 20120005504
    Abstract: For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state.
    Type: Application
    Filed: September 14, 2011
    Publication date: January 5, 2012
    Inventors: Takayuki FUKATANI, Yasutomo YAMAMOTO, Tomohiro KAWAGUCHI, Masanori TAKADA, Yoshiaki EGUCHI
  • Publication number: 20110307721
    Abstract: Proposed are a storage apparatus and a power consumption estimation method capable of easily and accurately estimating the power consumption of a physical drive without having to use a wattmeter. Operational information concerning a seek amount and a data transfer amount in the relevant hard disk drive which are internally recorded and retained by the respective hard disk drives is collected from each of the hard disk drives, and power consumption of each of the hard disk drives is estimated based on the acquired operational information of each of the hard disk drives.
    Type: Application
    Filed: March 5, 2010
    Publication date: December 15, 2011
    Applicant: HITACHI, LTD.
    Inventors: Katsumi Ouchi, Masanori Takada, Akira Yamamoto
  • Patent number: 8075213
    Abstract: A medium transport apparatus includes a feeding roller configured to rotate around a rotational axis. A guide rail extends along the rotational axis. A slider is supported by the guide rail and movable along the rotational axis. A rotatable pinch roller is configured to clamp medium between the feeding roller and the pinch roller to move the medium. A lever is connected to the pinch roller and movable to change a clamping state with respect to the medium between the feeding roller and the pinch roller. An arm is connected to the slider and configured to take an engaging position where the arm moves the lever to change the clamping state when the slider moves along the rotational axis and a standby position where the arm is not engaged with the lever when the slider moves along the rotational axis.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: December 13, 2011
    Assignee: Mimaki Engineering Co., Ltd.
    Inventors: Masanori Takada, Tadanori Ipponyari, Eiji Miyashita, Tetsuharu Ikeda, Akio Kobayashi
  • Publication number: 20110296117
    Abstract: Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.
    Type: Application
    Filed: April 6, 2009
    Publication date: December 1, 2011
    Applicant: HITACHI, LTD.
    Inventors: Hideaki Fukuda, Nobuyuki Minowa, Naoki Moritoki, Masanori Takada, Masato Shimizu
  • Publication number: 20110296129
    Abstract: A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Applicant: HITACHI, LTD.
    Inventors: Masahiro Arai, Hiroshi Hirayama, Masanori Takada, Hiroshi Kanayama, Hideaki Fukuda