Patents by Inventor Masao Kondo

Masao Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978786
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: May 7, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Publication number: 20240096824
    Abstract: A stacked semiconductor device capable of increasing heat dissipation comprises a first member and a second member. The first member includes a semiconductor substrate and a first electronic circuit. The first electronic circuit includes a semiconductor element provided on one surface of the semiconductor substrate. A second member is attached to a first surface, which is one surface of the first member. The second member includes a second electronic circuit including another semiconductor element. The second member is provided with a first opening that penetrates the second member in a thickness direction. A first conductor projection is coupled to the first electronic circuit. The first conductor projection protrudes from the first surface of the first member through the first opening of the second member to the outside of the first opening.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Satoshi GOTO, Takayuki TSUTSUI, Shinnosuke TAKAHASHI
  • Publication number: 20240096792
    Abstract: A semiconductor module comprises a first member including a semiconductor substrate made of a compound semiconductor and a first electronic circuit on the semiconductor substrate is mounted on a mounting surface of a module substrate, and a second member including a semiconductor layer formed of a single semiconductor thinner than the semiconductor substrate of the first member and a second electronic circuit on the semiconductor layer is bonded to an upper surface of the first member. First and second pads are respectively connected to the first electronic circuit on the first member and the second electronic circuit on the second member. A first wire connects the first pad and a substrate side pad. A second wire connects the second pad and a substrate side pad. An inter-member connection wire made of a conductor film on the first and second members connects the first and second electronic circuits.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi GOTO, Masao KONDO, Shigeki KOYA, Takayuki TSUTSUI
  • Publication number: 20240019935
    Abstract: A haptic device includes an external grasp body that is positioned on an outside, formed as a grasp portion of an imaginary object, and grasped by an operator, a motion detection unit that is provided in the external grasp body to detect a motion of the external grasp body, and an internal drive body that is provided in the external grasp body, connected to the external grasp body, and moves relative to the external grasp body on the basis of a result of the detection by the motion detection unit.
    Type: Application
    Filed: October 22, 2021
    Publication date: January 18, 2024
    Inventors: MASAO KONDO, JUNICHI SHIMIZU
  • Publication number: 20240014296
    Abstract: In a semiconductor device, plural cells are disposed side by side on a substrate in a first direction. Each of the plural cells includes a bipolar transistor, an emitter electrode contained in a base layer of the bipolar transistor as viewed from above, and a base electrode. The bipolar transistors of the plural cells are connected in parallel with each other. Among the plural cells, the breakdown resistance of at least one second cell, which is other than a first cell disposed at each end, is higher than that of the first cell. It is possible to provide a semiconductor device that can reduce the deterioration of the breakdown resistance when flip-chip mounting is employed, as well as when face-up mounting is employed.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki KOYA, Masao KONDO, Shaojun MA, Satoshi GOTO, Kenji SASAKI, Takayuki TSUTSUI, Kazuhito NAKAI
  • Patent number: 11871513
    Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 9, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Shigeki Koya, Kenji Sasaki
  • Patent number: 11855586
    Abstract: A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: December 26, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masao Kondo, Hidetoshi Matsumoto
  • Patent number: 11791782
    Abstract: A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: October 17, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Kiichiro Takenaka, Satoshi Tanaka, Takayuki Tsutsui
  • Patent number: 11784245
    Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: October 10, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Yasunari Umemoto, Shigeki Koya, Shinnosuke Takahashi, Masao Kondo
  • Patent number: 11769702
    Abstract: An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: September 26, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Yoshimitsu Takenouchi, Kenji Sasaki, Masao Kondo
  • Patent number: 11682355
    Abstract: The present technology relates to a display apparatus, a display control method, a portable terminal apparatus, and a program capable of representing various states of an apparatus in a limited region. A television receiver includes a display unit that displays a predetermined image, a communication unit that performs communication of image data with another image display apparatus, an indicator unit that is disposed at at least a part of surroundings of the display unit and includes an indicator which is turned on with predetermined luminance, and a control unit that turns on the indicator so as to correspond to a transmission operation of the image data in another image display apparatus. The present invention is applicable to, for example, a display apparatus such as a television receiver.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 20, 2023
    Assignee: Saturn Licensing LLC
    Inventors: Masao Kondo, Fumiya Matsuoka, Ken Yano, Hirotaka Tako
  • Patent number: 11646704
    Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current by subjecting the first signal to detection. The bias adjustment circuit controls the bias current such that a first current extracted from the bias circuit depends on a magnitude of the first signal.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 9, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Masao Kondo, Satoshi Tanaka
  • Patent number: 11626511
    Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 11, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 11509951
    Abstract: The present disclosure relates to a control device, a control method, an electronic device, and a program that enables an operation in a natural manner for switching between and remotely operating various control target devices. A plurality of control target devices emits infrared light codes each including a unique ID in a predetermined pattern. A user holds a controller and directs an infrared light receiving unit toward a control target device. At this time, a control state is established for the control target device specified by an infrared light code received by the controller. After the control state has been established, when a user rotates a main body of the controller, a control parameter in accordance with the amount of rotation is calculated, and a control command in accordance with the control parameter is transmitted to the control target device to control the control target device. The present disclosure can be applied to a remote controller.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 22, 2022
    Assignee: SONY CORPORATION
    Inventors: Yoshihito Ohki, Hirotaka Tako, Masao Kondo, Yusuke Tsujita, Yohei Nakajima, Daisuke Shiono, Miho Yamada, Masanori Matsushima, Hiroshi Nakayama, Seiji Suzuki, Kenichi Yamaura, Yoshiyasu Kubota
  • Patent number: 11502016
    Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 15, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Masahiro Shibata
  • Patent number: 11495563
    Abstract: Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 8, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Kenji Sasaki, Shigeki Koya, Shinnosuke Takahashi
  • Publication number: 20220271401
    Abstract: An axial lead extending on a principal surface of a flat tab includes a main body part having a diameter and a connection part. The connection part includes a first part located adjacent to the main body part and a second part located from the first part and the end part. The first part includes a weld part welded to the flat tab and has a first thickness less than the diameter. The second part includes a non-weld part not welded to the flat tab and has a second thickness equal to or less than the first thickness. The second part is formed by pressing the end part of the axial lead, the end part having been raised when resistance welding is performed on the axial lead and the flat tab.
    Type: Application
    Filed: December 14, 2021
    Publication date: August 25, 2022
    Applicant: FDK CORPORATION
    Inventors: Yuya IIDA, Yuki YAMANE, Masao KONDO
  • Publication number: 20220200542
    Abstract: A power amplifier comprising a first member and a second member including a compound semiconductor region joined to a first face of the first member including a semiconductor region. The second member includes an amplifier circuit including a compound semiconductor element, and multiple clamp diodes connected in multiple stages and between an output port of the amplifier circuit and ground. The first member includes a switch, connected between an extension point, which is a middle point of the multiple clamp diodes and the ground, a temperature sensor, and a switch control circuit which performs on-off control of the switch based on a result of measurement by the temperature sensor. The extension point is connected to the switch via a path including an inter-member connection wire on an interlayer insulating film from the first face of the first member to a surface of the second member.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Takayuki TSUTSUI, Masao KONDO
  • Publication number: 20220173702
    Abstract: A power amplifier circuit includes an amplification unit, a heating unit, and a control circuit. The amplification unit is configured to amplify a radio-frequency signal. The heating unit is provided adjacent to the amplification unit. The heating unit includes one or more transistors configured to generate heat that increases as the passing current increases. The control circuit is coupled to the one or more transistors. The control circuit is configured to increase the passing current when the environmental temperature is a predetermined threshold or lower.
    Type: Application
    Filed: October 21, 2021
    Publication date: June 2, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Yasunari UMEMOTO, Shaojun MA, Shinnosuke TAKAHASHI
  • Publication number: 20220124908
    Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Shigeki KOYA, Kenji SASAKI