Patents by Inventor Masao Kondo

Masao Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11509951
    Abstract: The present disclosure relates to a control device, a control method, an electronic device, and a program that enables an operation in a natural manner for switching between and remotely operating various control target devices. A plurality of control target devices emits infrared light codes each including a unique ID in a predetermined pattern. A user holds a controller and directs an infrared light receiving unit toward a control target device. At this time, a control state is established for the control target device specified by an infrared light code received by the controller. After the control state has been established, when a user rotates a main body of the controller, a control parameter in accordance with the amount of rotation is calculated, and a control command in accordance with the control parameter is transmitted to the control target device to control the control target device. The present disclosure can be applied to a remote controller.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 22, 2022
    Assignee: SONY CORPORATION
    Inventors: Yoshihito Ohki, Hirotaka Tako, Masao Kondo, Yusuke Tsujita, Yohei Nakajima, Daisuke Shiono, Miho Yamada, Masanori Matsushima, Hiroshi Nakayama, Seiji Suzuki, Kenichi Yamaura, Yoshiyasu Kubota
  • Patent number: 11502016
    Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 15, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Masahiro Shibata
  • Patent number: 11495563
    Abstract: Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 8, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Kenji Sasaki, Shigeki Koya, Shinnosuke Takahashi
  • Publication number: 20220271401
    Abstract: An axial lead extending on a principal surface of a flat tab includes a main body part having a diameter and a connection part. The connection part includes a first part located adjacent to the main body part and a second part located from the first part and the end part. The first part includes a weld part welded to the flat tab and has a first thickness less than the diameter. The second part includes a non-weld part not welded to the flat tab and has a second thickness equal to or less than the first thickness. The second part is formed by pressing the end part of the axial lead, the end part having been raised when resistance welding is performed on the axial lead and the flat tab.
    Type: Application
    Filed: December 14, 2021
    Publication date: August 25, 2022
    Applicant: FDK CORPORATION
    Inventors: Yuya IIDA, Yuki YAMANE, Masao KONDO
  • Publication number: 20220200542
    Abstract: A power amplifier comprising a first member and a second member including a compound semiconductor region joined to a first face of the first member including a semiconductor region. The second member includes an amplifier circuit including a compound semiconductor element, and multiple clamp diodes connected in multiple stages and between an output port of the amplifier circuit and ground. The first member includes a switch, connected between an extension point, which is a middle point of the multiple clamp diodes and the ground, a temperature sensor, and a switch control circuit which performs on-off control of the switch based on a result of measurement by the temperature sensor. The extension point is connected to the switch via a path including an inter-member connection wire on an interlayer insulating film from the first face of the first member to a surface of the second member.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Takayuki TSUTSUI, Masao KONDO
  • Publication number: 20220173702
    Abstract: A power amplifier circuit includes an amplification unit, a heating unit, and a control circuit. The amplification unit is configured to amplify a radio-frequency signal. The heating unit is provided adjacent to the amplification unit. The heating unit includes one or more transistors configured to generate heat that increases as the passing current increases. The control circuit is coupled to the one or more transistors. The control circuit is configured to increase the passing current when the environmental temperature is a predetermined threshold or lower.
    Type: Application
    Filed: October 21, 2021
    Publication date: June 2, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Yasunari UMEMOTO, Shaojun MA, Shinnosuke TAKAHASHI
  • Publication number: 20220124908
    Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Shigeki KOYA, Kenji SASAKI
  • Publication number: 20220101802
    Abstract: The present technology relates to a display apparatus, a display control method, a portable terminal apparatus, and a program capable of representing various states of an apparatus in a limited region. A television receiver includes a display unit that displays a predetermined image, a communication unit that performs communication of image data with another image display apparatus, an indicator unit that is disposed at at least a part of surroundings of the display unit and includes an indicator which is turned on with predetermined luminance, and a control unit that turns on the indicator so as to correspond to a transmission operation of the image data in another image display apparatus. The present invention is applicable to, for example, a display apparatus such as a television receiver.
    Type: Application
    Filed: August 9, 2021
    Publication date: March 31, 2022
    Applicant: Saturn Licensing LLC
    Inventors: Masao KONDO, Fumiya MATSUOKA, Ken YANO, Hirotaka TAKO
  • Patent number: 11289434
    Abstract: A semiconductor element includes a semiconductor substrate, first and second amplifiers provided on the semiconductor substrate and adjacently provided in a first direction, a first reference potential bump provided on a main surface of the semiconductor substrate, and connecting the first amplifier and a reference potential, a second reference potential bump provided on the main surface, being adjacent to the first reference potential bump in the first direction, and connecting the second amplifier and a reference potential, and a rectangular bump provided on the main surface, provided between the first and second reference potential bumps in a plan view, and formed such that a second width in a second direction orthogonal to the first direction is larger than a first width in the first direction. The second width is larger than a width of at least one of the first and second reference potential bumps in the second direction.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 29, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Yasunari Umemoto, Isao Obu, Masao Kondo, Yuichi Saito, Takayuki Tsutsui
  • Patent number: 11276689
    Abstract: A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 15, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Masao Kondo, Shigeki Koya, Shinnosuke Takahashi, Yasunari Umemoto, Isao Obu, Takayuki Tsutsui
  • Patent number: 11269587
    Abstract: The present disclosure relates to an information processing apparatus and an information processing method as well as a program that make it possible to control, by a partition provided on a boundary between two spaces, a visual shielding property and an auditory shielding property of a first space to a person in a second space in an interlocking relationship with each other in response to a distance between the person in the second space and the partition. A distance between the partition, which partitions the first space and the second space, and a person in the second space is measured, and transmittance of the partition and magnitude of output of audio in the first space to the second space are controlled in response to the measured distance. The present disclosure can be applied to a control apparatus for a partition section.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 8, 2022
    Assignee: SONY CORPORATION
    Inventors: Yoshihito Ohki, Miho Yamada, Hirotaka Tako, Masao Kondo, Yusuke Tsujita, Yohei Nakajima, Daisuke Shiono, Masanori Matsushima, Hiroshi Nakayama, Seiji Suzuki, Yoshiyasu Kubota, Kenichi Yamaura
  • Publication number: 20220059427
    Abstract: A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.
    Type: Application
    Filed: July 8, 2021
    Publication date: February 24, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Kenji SASAKI, Shigeki KOYA
  • Patent number: 11249629
    Abstract: An information processing apparatus includes a connection unit, a processing execution unit, a setting unit, and a controller. The connection unit is capable of connecting input apparatuses that output operation information for executing an operation for an image displayed on a screen. The processing execution unit is capable of executing processing corresponding to the operation information on the image. The setting unit sets one of the input apparatuses as a main input apparatus, and sets the other input apparatuses as secondary input apparatuses. The controller performs control such that execution of the processing for the image by the processing execution unit based on the operation information from the input apparatus set as the main input apparatus is validated, and execution of the processing for the image by the processing execution unit based on the operation information from the input apparatuses set as the secondary input apparatuses is invalidated.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: February 15, 2022
    Assignee: Sony Corporation
    Inventors: Masashi Kimoto, Shigeatsu Yoshioka, Yutaka Hasegawa, Masao Kondo
  • Patent number: 11240912
    Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 1, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Shigeki Koya, Kenji Sasaki
  • Publication number: 20220029004
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 27, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Patent number: 11197064
    Abstract: The present technology relates to a display device, a display control method, and a program that enable various states of the device to be expressed in a limited region. A television receiver set includes an indicator unit disposed at least in a part of a periphery of a display unit on which a predetermined image is displayed and including an indicator configured to be lit at a predetermined luminance, and a display control unit configured to perform control such that the predetermined image displayed on the display unit is associated with lighting of the indicator. The present invention can be applied to a display device such as a television receiver set.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: December 7, 2021
    Assignee: Saturn Licensing LLC
    Inventors: Masao Kondo, Ken Yano, Mayu Irimajiri
  • Patent number: 11190151
    Abstract: A power amplifier including a first transistor for amplifying and outputting a radio frequency signal, a second transistor, a third transistor for supplying a bias current, a first voltage supply circuit for supplying a lower voltage to a base of the third transistor as a temperature of a first diode is higher. The third transistor and the first transistor, or the third transistor and the second transistor, are disposed without another electronic element interposed therebetween. The third transistor is disposed such that a distance between the third transistor and the first transistor is smaller than a distance between the first voltage supply circuit and the first transistor, or a distance between the third transistor and the second transistor is smaller than a distance between the first voltage supply circuit and the second transistor.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 30, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Yuichi Saito
  • Publication number: 20210344304
    Abstract: A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Inventors: Masao Kondo, Hidetoshi Matsumoto
  • Patent number: 11164963
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: November 2, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Publication number: 20210327775
    Abstract: An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 21, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki KOYA, Yoshimitsu TAKENOUCHI, Kenji SASAKI, Masao KONDO