Abstract: A detecting circuit (REFH, CM11, LA1, TN1, RN1) which detects an overcurrent flowing through a power-MOS transistor (401) in an output stage to output a first signal (ITN1) is disposed in a first driving circuit (303H) on the side of a high-side driver. Another detecting circuit (REFL, CM21, LA2, TN2, RN2) which detects an overcurrent flowing through a power-MOS transistor (402) in the output-stage to output a second signal (ITN2) is disposed in a driving circuit (303L) on the side of a low-side driver. The first signal (ITN1) is converted to a third signal (ITT2) based on a negative power supply (VPP−), by a signal converting circuit. The third signal is added to the second signal. In response to the addition signal, a pulse signal to be input to the driving circuits (303H and 303L) is blocked.

Abstract: An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics.

Abstract: Differential integrator circuit integrates a differential between a difference between a signal supplied from a first signal source and a feedback signal of amplifier output and a difference between a signal supplied from a second signal source and a feedback signal of the amplifier output. The signal supplied from the second signal source is opposite in phase from the signal supplied from the first signal source. Thus, the integrator circuit outputs two integrated signals of different polarities. Comparator compares the two integrated signals from the integrator circuit to thereby output a PWM signal. First driver circuit amplifies the PWM signal and outputs the amplified PWM signal with inverted phase, and a second driver circuit amplifies the PWM signal and outputs the amplified PWM signal with noninverted phase. First switching circuit is driven by the output of the first driver circuit, while a second switching circuit is driven by the output of the second driver circuit.

Abstract: A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.

Abstract: The integrating circuit of the triangular wave generating circuit includes an operational amplifier and a capacitor. Switch elements are alternatively turned ON and capacitors are alternatively recharged by the currents flowing in constant-current circuits thus obtaining a triangular wave on an output terminal. In this practice, when the voltage on the output terminal reaches ±1 V, comparator circuits (41, 42) and a flip-flop including NAND gates change over the switch elements. The currents flowing in the constant-current circuits are controlled depending on the current flowing in a load circuit. The current flowing in the load circuit is controlled by a PLL circuit including a phase comparator circuit, a loop filter, an LPF, an operational amplifier and an FET. This provides an output triangular wave having the same frequency as a clock pulse (CK).

Abstract: A class D amplifier includes: an integrating circuit (1) which integrates an input signal; a flash A/D converter (2) which A/D converts an output signal of the integrating circuit; a waveform converting circuit (3) which produces a PWM signal based on an output of the flash A/D converter; a switching circuit which is includes a pair of MOS transistors (5, 6) connected between a first power source and a second power source, the junction point P of the pair of MOS transistors being connected to a loudspeaker (51); a driving circuit (4) which drives the pair of MOS transistors on the basis of the PWM signal; and a feedback resistor (RNF) which is connected between the junction point P and the input side of the integrating circuit, and negatively feeds back the output signal of the amplifier.

Abstract: An input signal (SIN) is inverted by an inverter (101), and the inverted input signal is entered into a tri-state type inverter (104). An output portion of this inverter is connected via a delay path (105) to an input portion of an operational amplifier (106). This operational amplifier owns a hysteresis characteristic with respect to a signal entered thereinto. An exclusive-OR gate circuit (103) controls to set the output state of the inverter to a low impedance state upon receipt of a signal (S11) obtained by inverting the input signal, and controls to set the output state of the inverter to a high impedance state upon receipt of a signal (S16) output from the operational amplifier. As a result, an amplitude of a signal (S15) is limited to a constant amplitude in response to the hysteresis characteristic of the operational amplifier (106), and a delay time is made constant.

Abstract: A complementary signal generating circuit (301) generates first complementary signals (S1, S2) from a PWM signal. A signal converting circuit (302) converts the first complementary signals to second complementary signals (S3, S4 or S5, S6) having a voltage component based on a negative power supply (VPP−). Among the second-complementary signals, the signals (S3, S4) are supplied to a driving circuit (305), and the signals (S5, S6) are supplied to a current driving circuit (303). In response to the signals (S5, S6), the current driving circuit outputs third complementary signals (H3, H4) having a current component that is directed toward the negative power supply (VPP−), to a driving circuit (304). As a result, the driving circuits (304, 305).complementarily drive power-MOS transistors (401, 402).

Abstract: An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.

Abstract: A pseudo-stereo circuit is provided which processes an input monophonic signal into stereophic audio signals. A phase-shift circuit shifts a phase of the input monophonic signal by a phase shift amount that depends upon a frequency of the monophonic signal, to produce an output signal having a gain with respect to the input monophonic signal which is equal to or larger than a predetermined level over an entire frequency band thereof, and reaches a peak at a frequency at which the phase shift amount of the output signal with respect to the input monophonic signal assumes a value equal or closer to −&pgr;. A mixing circuit produces a first mixed signal by mixing a signal obtained by inverting a phase of the output signal of the phase-shift circuit with the input monophonic signal by a first mixing ratio, and produces a second mixed signal obtained by mixing the output signal of the phase-shift circuit with the input monophonic signal by a second mixing ratio.

Abstract: A power-on/off reset circuit comprises a capacitor, a first transistor, a second transistor, a first current mirror circuit, a second current mirror circuit, and an inverter. In a power-on mode where the source voltage gradually increases in level, the capacitor is charged via the first transistor. The first current mirror circuit comprising a pair of transistors allows a current to flow therein in proportion to a potential of the capacitor. The second transistor converts the current to a voltage, which is input to the inverter to provide a first reset signal in the power-on mode. In a power-off mode where the source voltage gradually decreases in level, the second current mirror circuit comprising a pair of transistors temporarily increases the input voltage of the inverter to provide a second reset signal.

Abstract: Differential integrator circuit integrates a differential between a difference between a signal supplied from a first signal source and a feedback signal of amplifier output and a difference between a signal supplied from a second signal source and a feedback signal of the amplifier output. The signal supplied from the second signal source is opposite in phase from the signal supplied from the first signal source. Thus, the integrator circuit outputs two integrated signals of different polarities. Comparator compares the two integrated signals from the integrator circuit to thereby output a PWM signal. First driver circuit amplifies the PWM signal and outputs the amplified PWM signal with inverted phase, and a second driver circuit amplifies the PWM signal and outputs the amplified PWM signal with noninverted phase. First switching circuit is driven by the output of the first driver circuit, while a second switching circuit is driven by the output of the second driver circuit.

Abstract: A class D amplifier includes: an integrating circuit (1) which integrates an input signal; a flash A/D converter (2) which A/D converts an output signal of the integrating circuit; a waveform converting circuit (3) which produces a PWM signal based on an output of the flash A/D converter; a switching circuit which is includes a pair of MOS transistors (5, 6) connected between a first power source and a second power source, the junction point P of the pair of MOS transistors being connected to a loudspeaker (51); a driving circuit (4) which drives the pair of MOS transistors on the basis of the PWM signal; and a feedback resistor (RNF) which is connected between the junction point P and the input side of the integrating circuit, and negatively feeds back the output signal of the amplifier.

Abstract: A pulse-width modulation circuit comprises a comparator having hysteresis characteristics of positive feedback, and an integrator, whose integrated output is compared with an input signal to produce a pulse-width modulation (PWM) signal having an advanced phase characteristic due to differentiation of the input signal. A switching circuit amplifies the pulse-width modulation signal based on the positive and negative source voltages (VPX, VMX). The amplified pulse-width modulation signal is supplied to a speaker via an LC filter, and it is also negatively fed back to the pulse-width modulation circuit. Since the pulse-width modulation signal whose phase is advanced is transmitted through the LC filter, it is possible to reduce phase revolution in the output of the power amplifier circuit. Thus, it is possible to effect negative feedback on the pulse-width modulation signal in a stable manner.

Abstract: A current detection circuit applicable to a switching circuit using switching transistors to supply a prescribed load current to a load, comprises a sample-hold capacitor for temporarily holding a terminal voltage of the switching transistor that is turned on, and a switch that is inserted between the switching transistor and sample-hold capacitor and is controlled to be turned on in synchronization with the ON-timing of the switching transistor, wherein charged voltage of the sample-hold capacitor is detected as a detection voltage. An overcurrent detection circuit is constituted in such a way that the switching transistor is compulsorily turned off when the detection voltage exceeds reference voltage. The switching circuit may correspond to a pulse-width modulation (PWM) amplifier using a pair of a PMOS transistor and an NMOS transistor that are alternately turned on or off.

Abstract: An input signal from a signal source (10) is applied to an amplifier (20) via an input coupling capacitor (CIN). An output signal from the amplifier (20) is supplied to a headphone (30) via an output coupling capacitor (C1), and negatively fed back by a first negative feedback circuit configured by resistors (R2, R1), and a capacitor (CNF). A second negative feedback circuit configured by a capacitor (C2) and a resistor (R3) is disposed between the output of the capacitor (C1) and the terminal of the amplifier (20). When a capacitor which is sufficiently smaller in capacitance than the capacitor (C1) is used as the capacitor (C2), the capacitance of the capacitor (C1) can be made smaller than that of a capacitor used in the conventional art and the frequency characteristics in a low-frequency band can be enhanced.

Abstract: The present invention provides a high-accuracy and multi-bit D/A converter which can be produced using a CMOS process. A resistor string is formed of a plurality of resistors connected in series. A switch matrix has switch strings each formed of switches each having one end thereof connected to a corresponding one of junctions of the resistors and having respective other ends commonly connected to one of common junctions. A decoder turns on and off the switches of the switch strings according to more significant bits of data for conversion. A less significant bits-conversion circuit generates a voltage corresponding to less significant bits of the data for conversion and outputs the voltage. An operational amplifier carries out addition or subtraction of a voltage at each of the common junctions and an output from the less significant bits-conversion circuit.

Abstract: A power-on/off reset circuit comprises a capacitor, a first transistor, a second transistor, a first current mirror circuit, a second current mirror circuit, and an inverter. In a power-on mode where the source voltage gradually increases in level, the capacitor is charged via the first transistor. The first current mirror circuit comprising a pair of transistors allows a current to flow therein in proportion to a potential of the capacitor. The second transistor converts the current to a voltage, which is input to the inverter to provide a first reset signal in the power-on mode. In a power-off mode where the source voltage gradually decreases in level, the second current mirror circuit comprising a pair of transistors temporarily increases the input voltage of the inverter to provide a second reset signal.

Abstract: An electronic volume circuit is provided, which can be driven by a single power source and can therefore be formed by an LSI that can be fabricated in a simple manner using an oxide film and a junction process for a single power source. A first amplifying circuit attenuates the amplitude of a bipolar input signal and converts the attenuated input signal to a unipolar signal, and a variable resistor device controls the degree of attenuation of the first amplifying circuit based on an externally supplied signal.

Abstract: An A/D conversion apparatus is provided, which is capable of securing a wide dynamic range of A/D conversion with a simple construction through suitably switching the input gain of the input analog signal between predetermined levels. An input gain control device controls gain of an input signal based on a control signal. A &Dgr;&Sgr; modulator carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit. A detecting device detects a peak value of the input signal based on the data of one bit. A gain control device generates the control signal based on the peak value detected by the detecting device in a manner such that the input signal having the gain thereof controlled falls within a predetermined range.