Patents by Inventor Masaru Izumisawa
Masaru Izumisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130248979Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.Type: ApplicationFiled: September 11, 2012Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Masaru Izumisawa, Hiroshi Ohta, Hiroaki Yamashita
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Patent number: 8283720Abstract: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers.Type: GrantFiled: March 18, 2008Date of Patent: October 9, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yauto Sumi, Masaru Izumisawa, Wataru Sekine, Hiroshi Ohta, Shoichiro Kurushima
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Patent number: 8227854Abstract: A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.Type: GrantFiled: November 7, 2007Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Wataru Saito, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Patent number: 8058693Abstract: There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.Type: GrantFiled: December 18, 2009Date of Patent: November 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Endo, Masaru Izumisawa, Takuma Hara, Syotaro Ono, Yoshiro Baba
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Patent number: 8030706Abstract: A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part.Type: GrantFiled: August 12, 2009Date of Patent: October 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Miho Watanabe, Masaru Izumisawa, Yasuto Sumi, Hiroshi Ohta, Wataru Sekine, Wataru Saito, Syotaro Ono, Nana Hatano
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Patent number: 8013360Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.Type: GrantFiled: April 21, 2010Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Patent number: 7994006Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: GrantFiled: November 14, 2008Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7989910Abstract: A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.Type: GrantFiled: October 16, 2008Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masaru Izumisawa, Yasuto Sumi, Hiroshi Ohta, Wataru Sekine, Nana Hatano
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Patent number: 7919824Abstract: A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically.Type: GrantFiled: March 13, 2009Date of Patent: April 5, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Wataru Saito, Nana Hatano, Masaru Izumisawa, Yasuto Sumi, Hiroshi Ohta, Wataru Sekine, Miho Watanabe
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Publication number: 20100230750Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.Type: ApplicationFiled: May 27, 2010Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20100200936Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.Type: ApplicationFiled: April 21, 2010Publication date: August 12, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Publication number: 20100187598Abstract: There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.Type: ApplicationFiled: December 18, 2009Publication date: July 29, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi ENDO, Masaru IZUMISAWA, Takuma HARA, Syotaro ONO, Yoshiro BABA
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Patent number: 7759732Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.Type: GrantFiled: March 1, 2007Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Patent number: 7737469Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region.Type: GrantFiled: May 15, 2007Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Publication number: 20100038712Abstract: A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part.Type: ApplicationFiled: August 12, 2009Publication date: February 18, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Miho WATANABE, Masaru IZUMISAWA, Yasuto SUMI, Hiroshi OHTA, Wataru SEKINE, Wataru SAITO, Syotaro ONO, Nana HATANO
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Patent number: 7622771Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.Type: GrantFiled: May 19, 2008Date of Patent: November 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Wataru Saito, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta, Wataru Sekine
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Patent number: 7605426Abstract: A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side of the semiconductor substrate.Type: GrantFiled: November 1, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Masakatsu Takashita, Yasuto Sumi, Masaru Izumisawa, Hiroshi Ohta
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Publication number: 20090236697Abstract: A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically.Type: ApplicationFiled: March 13, 2009Publication date: September 24, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro ONO, Wataru SAITO, Nana HATANO, Masaru IZUMISAWA, Yasuto SUMI, Hiroshi OHTA, Wataru SEKINE, Miho WATANABE
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Publication number: 20090101974Abstract: A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.Type: ApplicationFiled: October 16, 2008Publication date: April 23, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Syotaro Ono, Masaru Izumisawa, Yasuto Sumi, Hiroshi Ohta, Wataru Sekine, Nana Hatano
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Publication number: 20090075433Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: ApplicationFiled: November 14, 2008Publication date: March 19, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka