Patents by Inventor Masaru Izumisawa

Masaru Izumisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030222327
    Abstract: A semiconductor device includes a first-first conductivity type semiconductor layer which includes a cell region portion and a junction terminating region portion, the junction terminating region portion being a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field; a second first conductivity type semiconductor layer which is formed on one surface of the first-first conductivity type semiconductor layer; a first main electrode which is electrically connected to the second-first conductivity type semiconductor layer; first-second conductivity type semiconductor layers which are formed in the cell region portion of the first-first conductivity type semiconductor layer in substantially vertical directions to the one surface of the first-first conductivity type semiconductor layer, respectively, and which are periodically disposed in a first direction which is an arbitrary direction paralle
    Type: Application
    Filed: March 17, 2003
    Publication date: December 4, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa
  • Publication number: 20020175368
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is formed in the depth direction along one side of the trench in the semiconductor layer and contacts the semiconductor substrate. A second region of the first conductivity type is formed in a surface area of the semiconductor layer and close to the trench and contacts the first region. A third region of the second conductivity type is formed in the surface area of the semiconductor layer. A fourth region of the first conductivity type is formed in a surface area of the third region. A gate insulation film and a gate electrode are provided on the surface of the third region between the second region and the fourth region.
    Type: Application
    Filed: May 22, 2002
    Publication date: November 28, 2002
    Inventors: Masaru Izumisawa, Shigeo Kouzuki, Shinichi Hodama