Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

Abstract: A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device, the device including a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction and a semiconductor pillar piercing the stacked structural unit in the first direction, the method includes: forming a stacked unit including a core material film alternately stacked with a sacrificial film on a major surface of a substrate perpendicular to the first direction; making a trench in the stacked unit, the trench extending in the first direction and a second direction in a plane perpendicular to the first direction; filling a filling material into the trench; removing the sacrificial film to form a hollow structural unit, the hollow structural unit including a post unit supporting the core material film on the substrate, the post unit being made of the filling material; and forming the stacked structural unit by stacking one of the insulating films and one of the el

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.

Abstract: A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

Abstract: A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.

Abstract: Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers.

Abstract: A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structures, first and second semiconductor pillars, first and second memory units, and a semiconductor connection portion. The stacked structures include electrode films and first inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is aligned with the first stacked structure in a second direction perpendicular to the first. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The first and second memory units are provided between the electrode films and the semiconductor pillar, respectively. The semiconductor connection portion connects the first and second semiconductor pillars and includes: an end connection portion; and a first protrusion having a side face continuous with a side face of the first semiconductor pillar.

Abstract: According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines.

Abstract: A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped semiconductor formed perpendicular to the substrate, a first gate insulating film formed around the first pillar shaped semiconductor, and a first gate electrode formed around the first gate insulating film, and a plurality of memory cells including a second pillar shaped semiconductor formed on the first pillar shaped semiconductor, the diameter of the first pillar shaped semiconductor being larger than the diameter of the second pillar shaped semiconductor at the part where the second pillar shaped semiconductor is connected to the first pillar shaped semiconductor, a first insulating film formed around the second pillar shaped semiconductor, a charge storage layer formed around the first insulating film, a second insulating film formed around the charge storage layer, and first to nth electrodes formed around the second i

Abstract: A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film.

Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Abstract: A memory string comprises: a pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer. A select transistor comprises: a second semiconductor layer extending from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer. The first semiconductor layer is formed continuously in an integrated manner with the second semiconductor layer. The first insulating layer is formed continuously in an integrated manner with the third insulating layer.

Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.