Patents by Inventor Masaru Kidoh

Masaru Kidoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8217446
    Abstract: Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Patent number: 8218358
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 8203884
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; a first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer to electrically connect the first and second semiconductor pillars; a connection portion conductive layer opposing the connection portion semiconductor layer; a memory layer, an inner insulating film, and an outer insulating film provided between the first and second semiconductor layers and the electrode films and between the connection portion semiconductor layer and the connection portion conductive layer. At least a portion of a face of the connection portion conductive layer opposing the outer insulating film is a curved surface having a recessed configuration on a side of the outer insulating film.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: June 19, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Hideaki Aochi
  • Patent number: 8199573
    Abstract: A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Tomoko Fujiwara, Megumi Ishiduki, Yosuke Komori, Yoshimasa Mikajiri, Shigeto Oota, Ryouhei Kirisawa, Hideaki Aochi
  • Patent number: 8198667
    Abstract: A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.
    Type: Grant
    Filed: December 25, 2008
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuji Kuniya, Yosuke Komori, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Hideaki Aochi
  • Patent number: 8193571
    Abstract: A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20120135593
    Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru KITO, Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Hiroyasu TANAKA, Megumi ISHIDUKI, Yosuke KOMORI, Hideaki AOCHI
  • Publication number: 20120135595
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.
    Type: Application
    Filed: February 3, 2012
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8189391
    Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaro Itagaki, Yoshihisa Iwata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Ryota Katsumata, Hideaki Aochi, Akihiro Nitayama, Takashi Maeda, Tomoo Hishida
  • Patent number: 8189371
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 8188530
    Abstract: A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conducti
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Ryota Katsumata, Hideaki Aochi, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 8178919
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: May 15, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Fujiwara, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 8178917
    Abstract: A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: May 15, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Hideaki Aochi, Megumi Ishiduki, Yasuyuki Matsuoka
  • Patent number: 8169826
    Abstract: A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoo Hishida, Yoshihisa Iwata, Megumi Ishiduki, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 8154068
    Abstract: Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Hideaki Aochi, Masaru Kito, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Masaru Kidoh, Yoshiaki Fukuzumi
  • Patent number: 8154103
    Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Tohiba
    Inventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
  • Patent number: 8148789
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8148769
    Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
  • Publication number: 20120068354
    Abstract: According to one embodiment, a semiconductor memory device includes a multilayer body, a second electrode film provided on the multilayer body, a second insulating film provided on the second electrode film, a semiconductor film, a memory film and a gate insulating film. At boundary between the inner surface of the second through hole and the inner surface of the third through hole, or on the inner surface of the second through hole, a step difference is formed so that an upper side from the step difference is thicker than a lower side from the step difference.
    Type: Application
    Filed: March 11, 2011
    Publication date: March 22, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyasu TANAKA, Megumi Ishiduki, Ryota Katsumata, Masaru Kidoh
  • Publication number: 20120068253
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory region and a non-memory region. The memory region includes a stacked structural body, a semiconductor pillar, a memory layer, an inner insulating film and an outer insulating film. The stacked structural body includes a plurality of electrode films stacked alternately along a first direction with a plurality of inter-electrode insulating films. The semiconductor pillar pierces the stacked structural body in the first direction. The memory layer is provided between the semiconductor pillar and each of the plurality of electrode films. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and each of the plurality of electrode films. The non-memory region is provided with the memory region along a second direction orthogonal to the first direction. The non-memory region includes an insulating part.
    Type: Application
    Filed: March 21, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeto Oota, Masaru Kidoh, Hideaki Aochi