Patents by Inventor Masaru Saito

Masaru Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090323376
    Abstract: A semiconductor device incorporates a resistor on a structure that uses diffusion layers for sustaining the breakdown voltage thereof to realizes a very resistive element that exhibits a high breakdown voltage and high electrical resistance, includes a spiral very resistive element buried in an interlayer insulator film. A first end of the very resistive element is connected to a drain electrode wiring and the second end of the very resistive element is grounded. An intermediate point of the very resistive element is connected to ae voltage comparator of a control IC. The semiconductor device according to the invention facilitates reducing the components parts costs, assembly costs and size of a switching power supply that includes a very resistive element.
    Type: Application
    Filed: August 4, 2009
    Publication date: December 31, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Masaru SAITO
  • Publication number: 20080117653
    Abstract: A semiconductor device incorporates a resistor on a structure that uses diffusion layers for sustaining the breakdown voltage thereof to realizes a very resistive element that exhibits a high breakdown voltage and high electrical resistance, includes a spiral very resistive element buried in an interlayer insulator film. A first end of the very resistive element is connected to a drain electrode wiring and the second end of the very resistive element is grounded. An intermediate point of the very resistive element is connected to ae voltage comparator of a control IC. The semiconductor device according to the invention facilitates reducing the components parts costs, assembly costs and size of a switching power supply that includes a very resistive element.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 22, 2008
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Masaru SAITO
  • Publication number: 20070221963
    Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.
    Type: Application
    Filed: March 24, 2007
    Publication date: September 27, 2007
    Applicant: C/O FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Masaru SAITO, Koji SONOBE
  • Publication number: 20070155144
    Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.
    Type: Application
    Filed: March 2, 2007
    Publication date: July 5, 2007
    Applicant: FUJI ELECTRIC HOLDING CO., LTD.
    Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
  • Patent number: 7195980
    Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: March 27, 2007
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
  • Patent number: 7056035
    Abstract: An optical module includes a package; an optical device housed in the package, and having a temperature-dependent characteristic; a thermo-module connected to the optical device to control its temperature and configured to heat or cool the optical device when supplied with a first electric current in one direction or a second electric current in a direction opposite to the first electric current, respectively; and a heating element disposed close to the optical device and configured to heat the optical device when supplied with an electric current.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: June 6, 2006
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Kaoru Iida, Takahiro Okada, Takashi Koseki, Masaru Saito, Jun Miyokawa, Toru Fukushima, Takeshi Aikiyo
  • Patent number: 7050360
    Abstract: To provide a wrist watch with a vibration function which can more enhance the vibration effect so that even when the user is, for example, sleeping deeply, the vibration function can effectively act on the user. The wrist watch with a vibration function comprises a watch case, a box part formed at an under surface of the watch case, at least one vibration motor received in the box such that a part of the vibration motor projects from the box part, a cover formed of a flexible material and adapted to cover for positioning the vibration motor, a bottom case serving as a lower surface and having a window formed in a part of the bottom case, and a vibration source received in the case and projecting from the window in a loosely fitted state.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: May 23, 2006
    Assignee: Kabushiki-Kaisya Tokyo Shinya
    Inventor: Masaru Saito
  • Publication number: 20050127439
    Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.
    Type: Application
    Filed: January 6, 2005
    Publication date: June 16, 2005
    Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
  • Patent number: 6853034
    Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: February 8, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
  • Patent number: 6844598
    Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: January 18, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Gen Tada, Masaru Saito
  • Patent number: 6818954
    Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuing a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: November 16, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Gen Tada, Masaru Saito
  • Publication number: 20040159856
    Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.
    Type: Application
    Filed: February 18, 2004
    Publication date: August 19, 2004
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Gen Tada, Masaru Saito
  • Patent number: 6740952
    Abstract: A semiconductor device includes a stable high withstand voltage lateral MISFET device which suppresses a gradual withstand voltage drop under high voltage and humidity conditions. In a MISFET device with a 700V breakdown drain voltage, the length of extension Mc (&mgr;m) of a field plate FP1 from the source side end of a thermal oxidization film, and the total insulating film thickness Tox (&mgr;m) directly below the extending tip of the field plate FP1, are greater than or equal to lower limit values Mcmin, Tcmin. As a result, even if there is growth in charge accumulation at the interface of the mold resin, the field strength at a point B and point C is always lower than at a point A, which suppresses a gradual withstand voltage drop and a gradual ON current drop, whereby it becomes possible to realize a withstand voltage of 700V.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: May 25, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
  • Patent number: 6728746
    Abstract: A computer system includes at least one real machine provided with a machine controller and/or a plurality of virtual machines provided with a machine controller and an operating system for a virtual machine, the real machine and the plurality of virtual machines are connected to a shared memory.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: April 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Murase, Sunao Takahira, Toshinori Hiraishi, Masaru Saito, Kenichiro Shimogawa, Katsunori Hiraoka, Koshi Horizaki, Kenichi Tsukamoto, Yumi Ochiai
  • Publication number: 20030179656
    Abstract: To provide a wrist watch with a vibration function which can more enhance the vibration effect so that even when the user is, for example, sleeping deeply, the vibration function can effectively act on the user. The wrist watch with a vibration function comprises a watch case, a box part formed at an under surface of the watch case, at least one vibration motor received in the box such that a part of the vibration motor projects from the box part, a cover formed of a flexible material and adapted to cover for positioning the vibration motor, a bottom case serving as a lower surface and having a window formed in a part of the bottom case, and a vibration source received in the case and projecting from the window in a loosely fitted state.
    Type: Application
    Filed: March 13, 2003
    Publication date: September 25, 2003
    Applicant: Kabushiki-Kaisya Tokyo Shinyu
    Inventor: Masaru Saito
  • Publication number: 20030165306
    Abstract: An optical module includes a package; an optical device housed in the package, and having a temperature-dependent characteristic; a thermo-module connected to the optical device to control its temperature and configured to heat or cool the optical device when supplied with a first electric current in one direction or a second electric current in a direction opposite to the first electric current, respectively; and a heating element disposed close to the optical device and configured to heat the optical device when supplied with an electric current.
    Type: Application
    Filed: November 27, 2002
    Publication date: September 4, 2003
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kaoru Iida, Takahiro Okada, Takashi Koseki, Masaru Saito, Jun Miyokawa, Toru Fukushima, Takeshi Aikiyo
  • Publication number: 20030122195
    Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.
    Type: Application
    Filed: December 3, 2002
    Publication date: July 3, 2003
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Gen Tada, Masaru Saito
  • Patent number: 6525390
    Abstract: The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: February 25, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Gen Tada, Akio Kitamura, Masaru Saito, Naoto Fujishima
  • Publication number: 20020145172
    Abstract: A semiconductor device includes a stable high withstand voltage lateral MISFET device which suppresses a gradual withstand voltage drop under high voltage and humidity conditions. In a MISFET device with a 700V breakdown drain voltage, the length of extension Mc (&mgr;m) of a field plate FP1 the source side end of a thermal oxidization film, and the total insulating film thickness Tox (&mgr;m) directly below the extending tip of the field plate FP1, are greater than or equal to lower limit values Mcmin, Tcmin. As a result, even if there is growth in charge accumulation at the interface of the mold resin, the field strength at a point B and point C is always lower than at a point A, which suppresses a gradual withstand voltage drop and a gradual ON current drop, whereby it becomes possible to realize a withstand voltage of 700V.
    Type: Application
    Filed: March 12, 2002
    Publication date: October 10, 2002
    Inventors: Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
  • Publication number: 20010048122
    Abstract: The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering.
    Type: Application
    Filed: February 27, 2001
    Publication date: December 6, 2001
    Inventors: Gen Tada, Akio Kitamura, Masaru Saito, Naoto Fujishima