Patents by Inventor Masaru Sugimoto

Masaru Sugimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11605712
    Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 14, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shimpei Yamaguchi, Atsushi Tsuboi, Atsushi Endo, Masaru Sugimoto, Hiroshi Yano, Yasushi Kodashima, Masanobu Igeta
  • Publication number: 20210375684
    Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masaru SUGIMOTO, Hiroshi YANO, Yasushi KODASHIMA, Masanobu IGETA
  • Publication number: 20210376123
    Abstract: A method including depositing a dielectric film on a substrate including stacked structures with recessed portions formed on side surfaces of each of the stacked structures, wherein the dielectric film is deposited so that the stacked structures are covered at a thickness which is equal to or less than half a width of the recessed portions; filling a trench or trenches that are located between the stacked structures with a sacrificial film; etching the sacrificial film along the stacked structures; etching the dielectric film so that the dielectric film is etched more than the sacrificial film; removing the sacrificial film; after the removing of the sacrificial film, depositing a dielectric film to a thickness equal to or less than half the width of the recessed portions; and etching the deposited dielectric film, on a condition that the deposited dielectric film remains in the recessed portions.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masanobu IGETA, Masaru SUGIMOTO, Luis FERNANDEZ
  • Publication number: 20210082669
    Abstract: A plasma processing apparatus includes a process container that forms a process space to accommodate a target substrate, and a first electrode and a second electrode disposed opposite each other inside the process container. The first electrode is an upper electrode and the second electrode is a lower electrode and configured to support the target substrate through a mount face. A correction ring is disposed to surround the target substrate placed on the mount face of the second electrode. The correction ring includes a combination of a first ring to be around the target substrate and a second ring arranged around or above the first ring. A power supply unit is configured to apply a first electric potential and a second electric potential respectively to the first ring and the second ring to generate a potential difference between the first and second rings. The power supply unit is configured to variably set the potential difference.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akira KOSHIISHI, Masaru SUGIMOTO, Kunihiko HINATA, Noriyuki KOBAYASHI, Chishio KOSHIMIZU, Ryuji OHTANI, Kazuo KIBI, Masashi SAITO, Naoki MATSUMOTO, Yoshinobu OHYA, Manabu IWATA, Daisuke YANO, Yohei YAMAZAWA, Hidetoshi HANAOKA, Toshihiro HAYAMI, Hiroki YAMAZAKI, Manabu SATO
  • Patent number: 10861678
    Abstract: A plasma etching apparatus includes a second electrode configured to support a target substrate thereon, a second RF power supply unit configured to apply a second RF power for providing a bias for ion attraction to the second electrode, and a control system including and an RF controller. The RF controller is configured to switch the second RF power supply unit between a continuous mode that executes continuous supply of the second RF power at a constant power level and a power modulation mode that executes modulation of the second RF power between a first power and a second power larger than the first power. The RF controller is preset to control the second RF power supply unit such that the second RF power supply unit is first operated in the continuous mode for plasma ignition and then is switched into the power modulation mode.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 8, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Akira Koshiishi, Noriyuki Kobayashi, Shigeru Yoneda, Kenichi Hanawa, Shigeru Tahara, Masaru Sugimoto
  • Patent number: 10854431
    Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 1, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ohya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Patent number: 10619229
    Abstract: An iron alloy powder consists of, when the entirety thereof is assumed to be 100 mass %, Cr: 2.5 mass % to 3.5 mass %, Mo: 0.4 mass % to 0.6 mass %, and Fe and inevitable impurities as the balance, a mixed powder consisting of 15 mass % to 40 mass % of the iron alloy powder, 1.2 mass % to 1.8 mass % of a copper powder, 0.5 mass % to 1.0 mass % of a graphite powder, and a pure iron powder as the balance when the entire mixed powder is assumed to be 100 mass % is compacted into a compact, and the compact is sintered while transforming a structure derived from the pure iron powder into a structure in which a ferritic structure and a pearlitic structure are mixed and transforming a structure derived from the iron alloy powder into a martensitic structure.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 14, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, FINE SINTER CO., LTD
    Inventors: Nobuyuki Shinohara, Yuki Kamo, Yoshihisa Ueda, Takanori Yoneda, Yusaku Yoshida, Masaru Sugimoto
  • Publication number: 20200111645
    Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 9, 2020
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akira KOSHIISHI, Masaru SUGIMOTO, Kunihiko HINATA, Noriyuki KOBAYASHI, Chishio KOSHIMIZU, Ryuji OHTANI, Kazuo KIBI, Masashi SAITO, Naoki MATSUMOTO, Yoshinobu OHYA, Manabu IWATA, Daisuke YANO, Yohei YAMAZAWA, Hidetoshi HANAOKA, Toshihiro HAYAMI, Hiroki YAMAZAKI, Manabu SATO
  • Patent number: 10546727
    Abstract: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 28, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ohya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Patent number: 10529539
    Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
  • Publication number: 20190115192
    Abstract: A plasma etching apparatus includes a second electrode configured to support a target substrate thereon, a second RF power supply unit configured to apply a second RF power for providing a bias for ion attraction to the second electrode, and a control system including and an RF controller. The RF controller is configured to switch the second RF power supply unit between a continuous mode that executes continuous supply of the second RF power at a constant power level and a power modulation mode that executes modulation of the second RF power between a first power and a second power larger than the first power. The RF controller is preset to control the second RF power supply unit such that the second RF power supply unit is first operated in the continuous mode for plasma ignition and then is switched into the power modulation mode.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Applicant: Tokyo Electron Limited
    Inventors: Akira Koshiishi, Noriyuki Kobayashi, Shigeru Yoneda, Kenichi Hanawa, Shigeru Tahara, Masaru Sugimoto
  • Patent number: 10229815
    Abstract: A plasma etching apparatus includes a first RF power supply unit configured to apply a first RF power for plasma generation to a first electrode or a second electrode disposed opposite to each other in a process container configured to be vacuum-exhausted, a second RF power supply unit configured to apply a second RF power for ion attraction to the second electrode, and a controller configured to control the second RF power supply unit. The second RF power supply unit includes a second RF power supply and a second matching unit. The controller is preset to control the second RF power supply unit to operate in a power modulation mode that executes power modulation in predetermined cycles between a first power and a second power, while controlling the second matching unit to switch a matching operation in synchronism with the power modulation.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: March 12, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Koshiishi, Noriyuki Kobayashi, Shigeru Yoneda, Kenichi Hanawa, Shigeru Tahara, Masaru Sugimoto
  • Patent number: 10213830
    Abstract: A sintered alloy is produced from mixed powder containing first hard particles, second hard particles, graphite particles, and iron particles. The first hard particles are Fe—Mo—Ni—Co—Mn—Si—C-based alloy particles, the second hard particles are Fe—Mo—Si-based alloy particles, the mixed powder contains 5 to 50 mass % of the first hard particles, 1 to 8 mass % of the second hard particles, and 0.5 to 1.5 mass % of the graphite particles, when total mass of the first hard particles, the second hard particles, the graphite particles, and the iron particles is set as 100 mass %.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 26, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, FINE SINTER CO., LTD
    Inventors: Nobuyuki Shinohara, Kimihiko Ando, Yoshihisa Ueda, Yusaku Yoshida, Masaru Sugimoto
  • Patent number: 10058922
    Abstract: The object of the present invention is to provide a compact for producing a sintered alloy which allows a sintered alloy obtained by sintering the compact to have improved mechanical strength and wear resistance, a wear-resistant iron-based sintered alloy, and a method for producing the same. The wear-resistant iron-based sintered alloy is produced by: forming a compact for producing a sintered alloy from a powder mixture containing a hard powder, a graphite powder, and an iron-based powder by powder compacting; and sintering the compact for producing a sintered alloy while diffusing C in the graphite powder of the compact for producing a sintered alloy in hard particles that constitute the hard powder. The hard particles contain 10% to 50% by mass of Mo, 3% to 20% by mass of Cr, and 2% to 15% by mass of Mn, with the balance made up of incidental impurities and Fe, and the hard powder and the graphite powder contained in the powder mixture account for 5% to 60% by mass and 0.5% to 2.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 28, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, FINE SINTER CO., LTD, SANYO SPECIAL STEEL CO., LTD
    Inventors: Nobuyuki Shinohara, Kimihiko Andou, Yoshihisa Ueda, Yusaku Yoshida, Masaru Sugimoto, Toshiyuki Sawada, Shingo Fukumoto
  • Patent number: 9950369
    Abstract: Mixed powder that contains first hard particles, second hard particles, graphite particles, and iron particles is used to manufacture a sintered alloy. The first hard particle is a Fe—Mo—Cr—Mn based alloy particle, the second hard particle is a Fe—Mo—Si based alloy particle. The mixed powder contains 5 to 50 mass % of the first hard particles, 1 to 8 mass % of the second hard particles, and 0.5 to 1.0 mass % of the graphite particles when total mass of the first hard particles, the second hard particles, the graphite particles, and the iron particles is set as 100 mass %.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: April 24, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, FINE SINTER CO., LTD, SANYO SPECIAL STEEL CO., LTD
    Inventors: Nobuyuki Shinohara, Kimihiko Ando, Yoshihisa Ueda, Yusaku Yoshida, Masaru Sugimoto, Toshiyuki Sawada, Shingo Fukumoto
  • Publication number: 20180080104
    Abstract: An iron alloy powder consists of, when the entirety thereof is assumed to be 100 mass %, Cr: 2.5 mass % to 3.5 mass %, Mo: 0.4 mass % to 0.6 mass %, and Fe and inevitable impurities as the balance, a mixed powder consisting of 15 mass % to 40 mass % of the iron alloy powder, 1.2 mass % to 1.8 mass % of a copper powder, 0.5 mass % to 1.0 mass % of a graphite powder, and a pure iron powder as the balance when the entire mixed powder is assumed to be 100 mass % is compacted into a compact, and the compact is sintered while transforming a structure derived from the pure iron powder into a structure in which a ferritic structure and a pearlitic structure are mixed and transforming a structure derived from the iron alloy powder into a martensitic structure.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 22, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, FINE SINTER CO., LTD
    Inventors: Nobuyuki SHINOHARA, Yuki KAMO, Yoshihisa UEDA, Takanori YONEDA, Yusaku YOSHIDA, Masaru SUGIMOTO
  • Publication number: 20180039571
    Abstract: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 8, 2018
    Inventors: Yukikazu MATSUO, Yasuyuki TANAKA, Masaru SUGIMOTO, Kyosaku NOBUNAGA
  • Patent number: 9811450
    Abstract: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: November 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukikazu Matsuo, Yasuyuki Tanaka, Masaru Sugimoto, Kyosaku Nobunaga
  • Patent number: 9805945
    Abstract: Disclosed is a method for selectively etching a first region made of silicon oxide to a second region made of silicon nitride. The method includes: performing a first sequence once or more to etch the first region; and performing a second sequence once or more to further etch the first region. The first sequence includes: a first step of generating plasma of a processing gas containing a fluorocarbon to form a fluorocarbon-containing deposit on a workpiece; and a second step of etching the first region by radicals of the fluorocarbon. The second sequence includes: a third step of generating plasma of a processing gas containing a fluorocarbon gas to form a fluorocarbon-containing deposit on a workpiece; and a fourth step of generating plasma of a processing gas containing oxygen gas and an inert gas in the processing container.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 31, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Hidaka, Soichiro Kimura, Masaru Sugimoto
  • Publication number: 20170225231
    Abstract: Mixed powder that contains first hard particles, second hard particles, graphite particles, and iron particles is used to manufacture a sintered alloy. The first hard particle is a Fe—Mo—Cr—Mn based alloy particle, the second hard particle is a Fe—Mo—Si based alloy particle. The mixed powder contains 5 to 50 mass % of the first hard particles, 1 to 8 mass % of the second hard particles, and 0.5 to 1.0 mass % of the graphite particles when total mass of the first hard particles, the second hard particles, the graphite particles, and the iron particles is set as 100 mass %.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 10, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, FINE SINTER CO., LTD, Sanyo Special Steel Co., Ltd.
    Inventors: Nobuyuki SHINOHARA, Kimihiko ANDO, Yoshihisa UEDA, Yusaku YOSHIDA, Masaru SUGIMOTO, Toshiyuki SAWADA, Shingo FUKUMOTO