Patents by Inventor Masaru Sugimoto
Masaru Sugimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7988816Abstract: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.Type: GrantFiled: June 21, 2005Date of Patent: August 2, 2011Assignee: Tokyo Electron LimitedInventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ooya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
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Patent number: 7951262Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.Type: GrantFiled: June 21, 2005Date of Patent: May 31, 2011Assignee: Tokyo Electron LimitedInventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
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Patent number: 7740737Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.Type: GrantFiled: June 21, 2005Date of Patent: June 22, 2010Assignee: Tokyo Electron LimitedInventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa
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Publication number: 20100126668Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.Type: ApplicationFiled: January 29, 2010Publication date: May 27, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Akira KOSHIISHI, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa
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Patent number: 7717589Abstract: A light emitting device comprises: an LED chip mounted in a recess formed in a mounting substrate; a wavelength converting member that is disposed so as to cover the recess and the edge area around the recess and that is excited by light emitted from the LED chip to emit light of a wavelength different from an excitation wavelength; and an emission control member disposed at a light output side of the wavelength converting member so as to allow emission of light coming from an area of the wavelength converting member that corresponds to the recess and to prevent emission of light coming from an area of the wavelength converting member that corresponds to the edge area around the recess. This can prevent variations in color between light emitted from the central part of the wavelength converting member and light emitted from the part of the wavelength converting member that is located on the edge area around the recess of the mounting substrate, thereby reducing unevenness of color on the irradiation surface.Type: GrantFiled: November 25, 2004Date of Patent: May 18, 2010Assignee: Panasonic Electric Works Co., Ltd.Inventors: Kouji Nishioka, Masaru Sugimoto, Hideyoshi Kimura, Ryoji Yokotani, Yutaka Iwahori, Takuma Hashmoto, Shinya Ishizaki, Satoshi Mori, Hiroyuki Sekii, Eiji Shiohama
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Patent number: 7495322Abstract: A light-emitting device (200) has a submount (100) and a plate for heat transfer (300) having a metallic plate (30). The submount (100) has a mount base (10), at least one light-emitting diode chip (5) mounted thereon and electrically conducting lines (12-17) formed on the mount base (10) to be connected electrically to the light-emitting diode chip (5). A first plane (11) of the mount base (10) of the submount (100) is bonded thermally to the first plate (300). For example, the plate is a circuit board having a metallic plate (30), and the submount (100) is bonded thermally to the metallic plate (30) of the one of the at least one plate (300). In an example, a second plate for heat transfer is also bonded thermally to a second plane of the mount base (100) for providing a plurality of heat transfer paths.Type: GrantFiled: May 26, 2004Date of Patent: February 24, 2009Assignee: Panasonic Electric Works Co., Ltd.Inventors: Takuma Hashimoto, Masaru Sugimoto, Ryoji Yokotani, Koji Nishioka, Yutaka Iwahori, Shinya Ishizaki, Toshiyuki Suzuki, Yoshiyuki Uchinono, Masahide Muto, Satoshi Mori, Hideyoshi Kimura
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Publication number: 20080110859Abstract: An upper electrode and a lower electrode are disposed opposite to each other in a process container configured to be vacuum-exhausted. The upper electrode is connected to a first RF power supply configured to apply a first RF power for plasma generation. The lower electrode is connected to a second RF power supply configured to apply a second RF power for ion attraction. The second RF power supply is provided with a controller preset to control the second RF power supply to operate in a power modulation mode that executes power modulation in predetermined cycles between a first power set to deposit polymers on a predetermined film on a wafer and a second power set to promote etching of the predetermined film on the wafer.Type: ApplicationFiled: October 4, 2007Publication date: May 15, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Akira Koshiishi, Noriyuki Kobayashi, Shigeru Yoneda, Kenichi Hanawa, Shigeru Tahara, Masaru Sugimoto
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Publication number: 20080105378Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing 02.Type: ApplicationFiled: December 20, 2007Publication date: May 8, 2008Applicant: TOKYO ELECTRON LIMITEDInventor: Masaru SUGIMOTO
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Patent number: 7326358Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing O2.Type: GrantFiled: September 27, 2005Date of Patent: February 5, 2008Assignee: Tokyo Electron LimitedInventor: Masaru Sugimoto
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Publication number: 20070163995Abstract: In etching an insulating film such as an SiOC film or the like, in order to suppress a diameter of a hole or a width of a groove, a pre-processing is performed before performing the etching. In the pre-processing, a processing gas containing CF4 gas and CH3F gas is converted into a plasma, and an opening size of an opening portion of a resist mask is decreased by depositing deposits at a sidewall thereof by using the plasma. Further, in etching the SiOC film, a processing gas containing CF4 gas, CH3F gas, and N2 gas is converted into a plasma by supplying a processing gas atmosphere by using a first high frequency wave for generating the plasma, wherein the electric power divided by a surface area of a substrate becomes over 1500 W/70685.8 mm2 (a surface area of a 300 mm wafer), and then the SiOC film is etched.Type: ApplicationFiled: December 6, 2006Publication date: July 19, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Masaru SUGIMOTO, Noriyuki Kobayashi, Masaharu Sugiyama
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Publication number: 20070085103Abstract: A light emitting device comprises: an LED chip mounted in a recess formed in a mounting substrate; a wavelength converting member that is disposed so as to cover the recess and the edge area around the recess and that is excited by light emitted from the LED chip to emit light of a wavelength different from an excitation wavelength; and an emission control member disposed at a light output side of the wavelength converting member so as to allow emission of light coming from an area of the wavelength converting member that corresponds to the recess and to prevent emission of light coming from an area of the wavelength converting member that corresponds to the edge area around the recess. This can prevent variations in color between light emitted from the central part of the wavelength converting member and light emitted from the part of the wavelength converting member that is located on the edge area around the recess of the mounting substrate, thereby reducing unevenness of color on the irradiation surface.Type: ApplicationFiled: November 25, 2004Publication date: April 19, 2007Applicant: MATSUSHITA ELECTRIC WORKS, LTD.Inventors: Kouji Nishioka, Masaru Sugimoto, Hideyoshi Kimura, Ryoji Yokotani, Yutaka Iwahori, Takuma Hashmoto, Shinya Ishizaki, Satoshi Mori, Hiroyuki Sekii, Eiji Shiohama
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Publication number: 20070007540Abstract: A light-emitting device (200) has a submount (100) and a plate for heat transfer (300) having a metallic plate (30). The submount (100) has a mount base (10), at least one light-emitting diode chip (5) mounted thereon and electrically conducting lines (12-17) formed on the mount base (10) to be connected electrically to the light-emitting diode chip (5). A first plane (11) of the mount base (10) of the submount (100) is bonded thermally to the first plate (300). For example, the plate is a circuit board having a metallic plate (30), and the submount (100) is bonded thermally to the metallic plate (30) of the one of the at least one plate (300). In an example, a second plate for heat transfer is also bonded thermally to a second plane of the mount base (100) for providing a plurality of heat transfer paths.Type: ApplicationFiled: May 26, 2004Publication date: January 11, 2007Applicant: Matsushita Electric Works, Ltd.Inventors: Takuma Hashimoto, Masaru Sugimoto, Ryoji Yokotani, Koji Nishioka, Yutaka Iwahori, Shinya Ishizaki, Toshiyuki Suzuki, Yoshiyuki Uchinono, Masahide Muto, Satoshi Mori, Hideyoshi Kimura
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Patent number: 7084435Abstract: A light-emitting device which uses and LED having a light-emitting element being placed on a package substrate. The light-emitting element has a light-extracting surface. A fluorescent element which is formed by dispersing a fluorescent material in a transparent substance and is placed face to face with the light-extracting surface of the light emitting element and comprises a clearance gap in between. The light-emitting element generates light of a certain wavelength that emanates through the light-extracting surface into the fluorescent element where the wavelength is changed. The device further comprises an optical element which receives light from the light-emitting element through the fluorescent element and directs the light to the outside of the device.Type: GrantFiled: January 6, 2003Date of Patent: August 1, 2006Assignee: Matsushita Electric Works, Ltd.Inventors: Masaru Sugimoto, Masao Yamaguchi, Takuma Hashimoto, Koji Nishioka, Ryoji Yokotani, Hideyoshi Kimura, Tadashi Murakami, Eiji Shiohama
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Patent number: 7079060Abstract: In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.Type: GrantFiled: February 3, 2005Date of Patent: July 18, 2006Assignee: Renesas Technology Corp.Inventors: Toshiaki Tarui, Masaru Sugimoto, Hisaya Mori, Teruhiko Funakura
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Publication number: 20060065630Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing O2.Type: ApplicationFiled: September 27, 2005Publication date: March 30, 2006Applicant: TOKYO ELECTRON LIMITEDInventor: Masaru Sugimoto
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Publication number: 20060066247Abstract: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a variable DC power supply to apply a DC voltage to the upper electrode, so as to cause the absolute value of a self-bias voltage on the surface thereof to be large enough to obtain a suitable sputtering effect on the surface, and to increase the plasma sheath length on the upper electrode side to generate predetermined pressed plasma.Type: ApplicationFiled: June 21, 2005Publication date: March 30, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Yoshinobu Ooya, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
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Publication number: 20060037703Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.Type: ApplicationFiled: June 21, 2005Publication date: February 23, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa, Hidetoshi Hanaoka, Toshihiro Hayami, Hiroki Yamazaki, Manabu Sato
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Publication number: 20060037701Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.Type: ApplicationFiled: June 21, 2005Publication date: February 23, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Akira Koshiishi, Masaru Sugimoto, Kunihiko Hinata, Noriyuki Kobayashi, Chishio Koshimizu, Ryuji Ohtani, Kazuo Kibi, Masashi Saito, Naoki Matsumoto, Manabu Iwata, Daisuke Yano, Yohei Yamazawa
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Patent number: 6954079Abstract: The interface circuit includes n buffer circuits, switches for connecting an external pin of a tester to input nodes of n buffer circuits and connecting output nodes of n buffers respectively to n DUTs when a signal is provided from the tester to n DUTs, and successively connecting n DUTs to the external pin of the tester by a prescribed time period when voltage-ampere characteristics of n DUTs are measured. Therefore the number of devices that can be measured by the tester at a time can be increased by n times. As a result, the test cost can be reduced and the test accuracy can be improved.Type: GrantFiled: June 17, 2003Date of Patent: October 11, 2005Assignee: Renesas Technology Corp.Inventors: Masaru Sugimoto, Teruhiko Funakura, Hidekazu Nagasawa
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Publication number: 20050179576Abstract: In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.Type: ApplicationFiled: February 3, 2005Publication date: August 18, 2005Inventors: Toshiaki Tarui, Masaru Sugimoto, Hisaya Mori, Teruhiko Funakura