Patents by Inventor Masaru Takaishi

Masaru Takaishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040185659
    Abstract: A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film so as to fill the contact hole on the surface of the semiconductor substrate, a step of removing the part of the silicon-containing thin film outside the contact hole, a step of forming an aluminum-containing thin film on the surface of the semiconductor substrate after completing the step of removing the part of the silicon-containing substrate, and a step of heating the semiconductor substrate on which the aluminum-containing thin film is formed to such a temperature as to cause silicon to diffuse with respect to aluminum.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Inventor: Masaru Takaishi
  • Publication number: 20040185660
    Abstract: A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film in a region having a predetermined area including the inner surface of the contact hole on the surface of the semiconductor substrate, an step of forming an aluminum-containing thin film on the surface of the semiconductor substrate on which the silicon-containing thin film is formed, and a step of heating the semiconductor substrate on which the aluminum-containing thin film is formed to such a temperature as to cause silicon to diffuse with respect to aluminum.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Inventor: Masaru Takaishi
  • Publication number: 20040150000
    Abstract: A semiconductor device, including: a semiconductor chip having a polarity; and a plurality of protection diodes connected in series with polarities thereof being arranged in the same direction, the protection diodes and the semiconductor chip being connected in parallel with the polarities of the protection diodes being arranged in the same direction as the arrangement of polarities of the semiconductor chip.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 5, 2004
    Inventors: Masaru Takaishi, Hiroyuki Tamada
  • Patent number: 6649973
    Abstract: A channel diffusion area (2) for forming a channel region (2a) is placed on a semiconductor layer (1), a source area (3) is formed on this area and a source electrode (7) is formed on the surface of this source area by a metal film. Then, the metal of the source electrode is allowed to spike into the source area and the channel diffusion area to form an alloy layer (7a) with the semiconductor layer, and through this alloy layer, the source electrode is made in ohmic contact with both of the source area and the channel diffusion area. As a result, it is possible to obtain a semiconductor device with an insulated gate-driving element having a construction which makes it possible to minimize the on-resistance by increasing the gate width, using the chip area of the same size, and consequently to provide a greater current.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: November 18, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 6541827
    Abstract: An n-type semiconductor layer, for example, is provided to be a drain region (1). A plurality of p-type diffusion regions (body regions) are formed regularly on the surface of the semiconductor layer. And an n-type diffusion region is formed, as a source (3), on the surface of each of the plurality of p-type body regions (2), so that a channel region (8) is formed in a part between the source and the drain regions for a transistor cell. On the surface of the transistor cells, provided is a gate electrode (5) via an insulator film (4), and this gate electrode is patterned in a certain shape by removing portions above where adjoining three or four of said cells are bordering on each other without including any part of said channel regions (8). Those portions are referred to as removed portions (10).
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: April 1, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Publication number: 20030057497
    Abstract: A plurality of transistor cells (T) are arranged in the semiconductor layer (4). Ring-shaped p-type layers (1b) and n-type layers (1a) composed of polysilicon film are formed alternately on an insulating layer (6) in an outer side than the plurality of transistor cells (T) (the peripheral portion of chip), thereby forming a protective diode (1). The most outer layer of the protective diode (1) is contacted to the gate wiring (2) composed of metal film such as Al, which is formed circularly on the most external layer, and the most inner layer is contacted to the source wiring composed of metal layer, thereby the protective diode is connected between the gate and source of a transistor. As a result of this, the semiconductor device with the protective diode which has the small series resistance, can be formed without enlarging chip area and by using unoccupied space of chip, and realize protection function sufficiently, can be obtained.
    Type: Application
    Filed: November 6, 2001
    Publication date: March 27, 2003
    Inventors: Syouji Higashida, Masaru Takaishi
  • Publication number: 20020190313
    Abstract: A semiconductor device has a cell region where transistor cells of a trench structure are arranged in a matrix form, in which a recessed trench is formed in a semiconductor layer, a gate oxide film is formed inside the recessed trench, and a gate electrode formed of polysilicon is disposed inside the recessed trench. To have contact with a gate wiring formed of a metal film, a gate pad disposed continuously to the gate electrode is placed inside a recessed part formed in the same depth as the recessed trench. Consequently, many transistor cells of the trench structure are formed in a matrix form. Even in a semiconductor device where the gate wiring formed of a metal film is contacted with the gate electrode, a semiconductor device of a structure allowing gate voltage to be increased sufficiently can be obtained.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 19, 2002
    Inventors: Masaru Takaishi, Koichi Kitaguro, Hiroki Takada
  • Publication number: 20020142548
    Abstract: A channel diffusion area (2) for forming a channel region (2a) is placed on a semiconductor layer (1), a source area (3) is formed on this area and a source electrode (7) is formed on the surface of this source area by a metal film. Then, the metal of the source electrode is allowed to spike into the source area and the channel diffusion area to form an alloy layer (7a) with the semiconductor layer, and through this alloy layer, the source electrode is made in ohmic contact with both of the source area and the channel diffusion area. As a result, it is possible to obtain a semiconductor device with an insulated gate-driving element having a construction which makes it possible to minimize the on-resistance by increasing the gate width, using the chip area of the same size, and consequently to provide a greater current.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 3, 2002
    Inventor: Masaru Takaishi