Patents by Inventor Masashi Horiguchi
Masashi Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10289145Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.Type: GrantFiled: April 30, 2018Date of Patent: May 14, 2019Assignee: Renesas Electronics CorporationInventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
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Patent number: 10152078Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.Type: GrantFiled: June 27, 2016Date of Patent: December 11, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
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Publication number: 20180253118Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.Type: ApplicationFiled: April 30, 2018Publication date: September 6, 2018Inventors: Shinya SANO, Masashi HORIGUCHI, Takahiro MIKI, Mitsuru HIRAKI
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Patent number: 9989985Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.Type: GrantFiled: December 22, 2016Date of Patent: June 5, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
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Publication number: 20170139436Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (Al) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.Type: ApplicationFiled: December 22, 2016Publication date: May 18, 2017Inventors: Shinya SANO, Masashi HORIGUCHI, Takahiro MIKI, Mitsuru HIRAKI
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Patent number: 9628021Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.Type: GrantFiled: February 15, 2016Date of Patent: April 18, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
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Patent number: 9564805Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.Type: GrantFiled: April 9, 2012Date of Patent: February 7, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
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Publication number: 20160306377Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Shinya SANO, Yasuhiko TAKAHASHI, Masashi HORIGUCHI
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Patent number: 9436195Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.Type: GrantFiled: October 20, 2014Date of Patent: September 6, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
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Patent number: 9405306Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.Type: GrantFiled: October 20, 2014Date of Patent: August 2, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
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Publication number: 20160164461Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
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Patent number: 9360381Abstract: A semiconductor device with improved temperature detection accuracy includes a coefficient calculation circuitry which calculates a plurality of N-th order coefficients, where N is an integer equal to or greater than one, of a correction function as an N-th order approximation of a characteristic function which relates temperature data measured by the temperature sensor and the actual temperature. The coefficient calculation circuitry uses N+1 pieces of the temperature data including a theoretical value at absolute zero in the characteristic function and N measured values of the temperature data measured by the temperature sensor unit at N points of temperature. A corrected temperatures are output using the correction function with the calculated coefficients and measured temperature values.Type: GrantFiled: April 4, 2012Date of Patent: June 7, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Arisaka, Takayasu Ito, Masashi Horiguchi
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Patent number: 9300248Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.Type: GrantFiled: April 28, 2014Date of Patent: March 29, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
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Publication number: 20150357248Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI
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Publication number: 20150326209Abstract: The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode.Type: ApplicationFiled: July 18, 2015Publication date: November 12, 2015Inventors: Osamu Ozawa, Masashi Horiguchi, Takayasu Ito
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Patent number: 9111909Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: GrantFiled: February 10, 2014Date of Patent: August 18, 2015Assignee: Tessera Advanced Technologies, Inc.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Patent number: 9093952Abstract: The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode.Type: GrantFiled: July 26, 2013Date of Patent: July 28, 2015Assignee: Renesas Electronics CorporationInventors: Osamu Ozawa, Masashi Horiguchi, Takayasu Ito
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Publication number: 20150035588Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.Type: ApplicationFiled: October 20, 2014Publication date: February 5, 2015Inventors: Shinya SANO, Yasuhiko TAKAHASHI, Masashi HORIGUCHI
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Patent number: 8866539Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.Type: GrantFiled: June 7, 2013Date of Patent: October 21, 2014Assignee: Renesas Electronics CorporationInventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
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Publication number: 20140252495Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: ApplicationFiled: February 10, 2014Publication date: September 11, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI