Patents by Inventor Masashi Horiguchi

Masashi Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10289145
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
  • Patent number: 10152078
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
  • Publication number: 20180253118
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Application
    Filed: April 30, 2018
    Publication date: September 6, 2018
    Inventors: Shinya SANO, Masashi HORIGUCHI, Takahiro MIKI, Mitsuru HIRAKI
  • Patent number: 9989985
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 5, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
  • Publication number: 20170139436
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (Al) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Application
    Filed: December 22, 2016
    Publication date: May 18, 2017
    Inventors: Shinya SANO, Masashi HORIGUCHI, Takahiro MIKI, Mitsuru HIRAKI
  • Patent number: 9628021
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: April 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Patent number: 9564805
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: February 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
  • Publication number: 20160306377
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: Shinya SANO, Yasuhiko TAKAHASHI, Masashi HORIGUCHI
  • Patent number: 9436195
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: September 6, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
  • Patent number: 9405306
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: August 2, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
  • Publication number: 20160164461
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Patent number: 9360381
    Abstract: A semiconductor device with improved temperature detection accuracy includes a coefficient calculation circuitry which calculates a plurality of N-th order coefficients, where N is an integer equal to or greater than one, of a correction function as an N-th order approximation of a characteristic function which relates temperature data measured by the temperature sensor and the actual temperature. The coefficient calculation circuitry uses N+1 pieces of the temperature data including a theoretical value at absolute zero in the characteristic function and N measured values of the temperature data measured by the temperature sensor unit at N points of temperature. A corrected temperatures are output using the correction function with the calculated coefficients and measured temperature values.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Arisaka, Takayasu Ito, Masashi Horiguchi
  • Patent number: 9300248
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 29, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Publication number: 20150357248
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI
  • Publication number: 20150326209
    Abstract: The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode.
    Type: Application
    Filed: July 18, 2015
    Publication date: November 12, 2015
    Inventors: Osamu Ozawa, Masashi Horiguchi, Takayasu Ito
  • Patent number: 9111909
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: August 18, 2015
    Assignee: Tessera Advanced Technologies, Inc.
    Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
  • Patent number: 9093952
    Abstract: The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: July 28, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Ozawa, Masashi Horiguchi, Takayasu Ito
  • Publication number: 20150035588
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Inventors: Shinya SANO, Yasuhiko TAKAHASHI, Masashi HORIGUCHI
  • Patent number: 8866539
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
  • Publication number: 20140252495
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Application
    Filed: February 10, 2014
    Publication date: September 11, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI