Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.

Abstract: A data transfer method is executed to transit a three-state transmitting circuit from a high-impedance state into a data output state, transmit a preamble (dummy data) onto a bus, and sequentially transmit the essential data. The shortening of a waveform caused in the first data piece after the transition from the high-impedance state into the data output state is executed against the preamble and no shortening of a waveform is not brought about in the essential data subsequent to the preamble. This makes it possible to exclude the limitation on speeding up the data transfer imposed by the shortening of the waveform.

Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Abstract: The present invention provides a semiconductor device capable of realizing power saving and improvement in reliability or reduction in area. A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is shut down. Voltage of the internal power supply in which power is shut down is generated from voltage of an external power supply by using a regulator circuit. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential.

Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

Abstract: A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements.