Patents by Inventor Masashi Horiguchi
Masashi Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8106678Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.Type: GrantFiled: December 23, 2009Date of Patent: January 31, 2012Assignee: Elpida Memory, Inc.Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
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Patent number: 8085566Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.Type: GrantFiled: November 23, 2010Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Masashi Horiguchi, Mitsuru Hiraki
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Patent number: 8073643Abstract: A semiconductor device which includes a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down, and an internal voltage determining circuit for determining the voltage of the internal power supply in which power is shut down. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When the power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, the increased voltage of the internal power supply is determined by the internal voltage determining circuit, operation of a circuit block is started, and the switch is turned on.Type: GrantFiled: May 18, 2008Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Takayasu Ito, Mitsuru Hiraki, Masashi Horiguchi, Toyohiro Shimogawa
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Patent number: 8059938Abstract: A picture recording apparatus which can record a picture on a write-once medium having an element which specifies a first size on a recording area assigned to data saving in edit processing, and an element which subtracts the first size from a remaining amount of recording area in the write-once medium to calculate a second size secured for recording, characterized in that a recording size is managed using the second size as an upper limit of a recordable size, and that an editing area is secured using the first size as a lower limit.Type: GrantFiled: October 3, 2005Date of Patent: November 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masataka Moteki, Seigo Ito, Masao Kubo, Masashi Horiguchi, Yukiyoshi Fujishiro
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Publication number: 20110261639Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.Type: ApplicationFiled: June 30, 2011Publication date: October 27, 2011Inventors: Takesada Akiba, Shigeki Ueda, Toshikazu Tachibana, Masashi Horiguchi
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Patent number: 8031546Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: February 23, 2010Date of Patent: October 4, 2011Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 7995417Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.Type: GrantFiled: September 15, 2010Date of Patent: August 9, 2011Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Takesada Akiba, Shigeld Ueda, Toshikazu Tachibana, Masashi Horiguchi
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Publication number: 20110115461Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.Type: ApplicationFiled: November 23, 2010Publication date: May 19, 2011Inventors: Masashi Horiguchi, Mitsuru Hiraki
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Publication number: 20110032777Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.Type: ApplicationFiled: September 15, 2010Publication date: February 10, 2011Inventors: Takesada Akiba, Shigeld Ueda, Toshikazu Tachibana, Masashi Horiguchi
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Patent number: 7876589Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.Type: GrantFiled: December 30, 2009Date of Patent: January 25, 2011Assignee: Renesas Electronics CorporationInventors: Masashi Horiguchi, Mitsuru Hiraki
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Publication number: 20110012180Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: ApplicationFiled: July 19, 2010Publication date: January 20, 2011Applicant: RENESAS TECHNOLOGY CORP.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Publication number: 20100327841Abstract: The present invention provides a technique for reducing current consumption in a reference voltage forming circuit without a significant increase in area while suppressing considerable degradative difference in reference voltage accuracy between a normal operation mode and a standby mode. In the standby mode, by using a clock signal fed from an oscillator circuit, the frequency-division control circuit produces an enable signal VREFON for determining ON/OFF states of the reference voltage generator circuit, the reference voltage forming circuit, and the capacitance charging regulator, and also produces a sampling/holding signal CHOLDSW for performing control so that a holding capacitor CH in a holding capacitance circuit is charged during an ON period of the reference voltage generator circuit, the reference voltage forming circuit, and the capacitance charging regulator, and so that any paths other than a leak current path are made unavailable to the holding capacitor CH during an OFF period thereof.Type: ApplicationFiled: June 8, 2010Publication date: December 30, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takayasu ITO, Mitsuru HIRAKI, Masashi HORIGUCHI
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Patent number: 7821862Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.Type: GrantFiled: September 26, 2007Date of Patent: October 26, 2010Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Takesada Akiba, Shigeki Ueda, Toshikazu Tachibana, Masashi Horiguchi
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Patent number: 7781814Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: GrantFiled: May 19, 2008Date of Patent: August 24, 2010Assignee: Renesas Technology Corp.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Patent number: 7750668Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: October 31, 2007Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Publication number: 20100149883Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: ApplicationFiled: February 23, 2010Publication date: June 17, 2010Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20100109446Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.Type: ApplicationFiled: December 30, 2009Publication date: May 6, 2010Inventors: Masashi Horiguchi, Mitsuru Hiraki
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Publication number: 20100109702Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.Type: ApplicationFiled: December 23, 2009Publication date: May 6, 2010Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
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Patent number: 7693000Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: October 15, 2008Date of Patent: April 6, 2010Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., LtdInventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 7692997Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.Type: GrantFiled: July 1, 2008Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Masashi Horiguchi, Mitsuru Hiraki