Patents by Inventor Masashi Sahara

Masashi Sahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070246780
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Application
    Filed: March 19, 2007
    Publication date: October 25, 2007
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Publication number: 20070228574
    Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.
    Type: Application
    Filed: May 31, 2007
    Publication date: October 4, 2007
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Patent number: 7241685
    Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: July 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hideo Miura, Shinji Nishihara, Masashi Sahara
  • Publication number: 20070066050
    Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge to be suppressed to a low level, and the short-circuiting-failure between adjacent wirings to be suppressed or prevented.
    Type: Application
    Filed: November 21, 2006
    Publication date: March 22, 2007
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Patent number: 7189637
    Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge can be suppressed to a low level, and the short-circuiting failure between adjacent wirings can be suppressed or prevented.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: March 13, 2007
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Publication number: 20060289998
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: July 20, 2006
    Publication date: December 28, 2006
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Patent number: 7132341
    Abstract: In a high-performance semiconductor integrated circuit, the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM. A gate electrode G is formed on semiconductor substrate 1 and n+-type semiconductor regions 17 (source/drain regions) are formed in the semiconductor substrate on both sides of this gate electrode. Within the same apparatus and under near-vacuum conditions, a depth of 2.5 nm or less is etched away from the surfaces of the source/drain regions and gate electrode, a film of Co is then formed on the source/drain regions, and thermal processing is applied to form CoSi2 layer 19a. As a result, current leakage in the memory cell can be prevented and this method can be applied to semiconductor integrated circuit devices that have low current consumption or are battery-driven.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: November 7, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masashi Sahara, Fumiaki Endo, Masanori Kojima, Katsuhiro Uchimura, Hideaki Kanazawa, Masakazu Sugiura
  • Patent number: 7102223
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: September 5, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Patent number: 7064437
    Abstract: There is provided a semiconductor device having high reliability, high yield, and such a interconnection structure as short hardly occurs. The semiconductor device comprises a semiconductor substrate, metal conductors formed on a side of a main face of the substrate which metal conductors contain aluminum as main constituent thereof and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: June 20, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Patent number: 6897570
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: May 24, 2005
    Assignee: Renesas Technology, Corporation
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Patent number: 6856021
    Abstract: A semiconductor device is provided which includes a semiconductor substrate, metal conductors formed on a side of a main face of the substrate, which metal conductors contain aluminum as a main constituent thereof, and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: February 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Publication number: 20040235289
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 25, 2004
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Patent number: 6784549
    Abstract: In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: August 31, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Patent number: 6780757
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Publication number: 20040121571
    Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of the manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge can be suppressed low, and the short-circuiting failure between adjacent wirings can be suppressed or prevented.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Inventors: Ken Uchikoshi, Naokatsu Suwanai, Atsushi Tachigami, Katsuhiko Hotta, Masashi Sahara, Kazuhiko Sato
  • Publication number: 20030230809
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Application
    Filed: January 9, 2003
    Publication date: December 18, 2003
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Publication number: 20030199161
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Application
    Filed: May 7, 2003
    Publication date: October 23, 2003
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Publication number: 20030170980
    Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
    Type: Application
    Filed: March 18, 2003
    Publication date: September 11, 2003
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hideo Miura, Shinji Nishihara, Masashi Sahara
  • Patent number: 6617691
    Abstract: The object of the invention is to provide such a highly reliable semiconductor device as no defect such as the breakage of a tungsten conductor occurs. This object is achieved by the following means, i.e., a molybdenum film, a tungsten film and another molybdenum film are deposited in this order on an interlayer dielectric film formed on a silicon substrate.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Nakajima, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Shinji Nishihara, Masashi Sahara, Kentaro Yamada, Masayuki Suzuki
  • Publication number: 20030160267
    Abstract: In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
    Type: Application
    Filed: March 25, 2003
    Publication date: August 28, 2003
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara