Patents by Inventor Masashi Sahara

Masashi Sahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6583049
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: June 24, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Microcomputer System Ltd.
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Patent number: 6548904
    Abstract: In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: April 15, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Patent number: 6545362
    Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hideo Miura, Shinji Nishihara, Masashi Sahara
  • Patent number: 6538329
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: March 25, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Microcomputer System Ltd.
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Publication number: 20030020167
    Abstract: In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
    Type: Application
    Filed: September 24, 2002
    Publication date: January 30, 2003
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Publication number: 20030015801
    Abstract: The object of the invention is to provide such a highly reliable semiconductor device as no defect such as the breakage of a tungsten conductor occurs. This object is achieved by the following means, i.e., a molybdenum film, a tungsten film and another molybdenum film are deposited in this order on an interlayer dielectric film formed on a silicon substrate.
    Type: Application
    Filed: September 24, 2002
    Publication date: January 23, 2003
    Inventors: Takashi Nakajima, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Shinji Nishihara, Masashi Sahara, Kentaro Yamada, Masayuki Suzuki
  • Patent number: 6503803
    Abstract: Disclosed is a method of fabricating a semiconductor device including forming an insulating film on a silicon substrate; forming a contact hole in the insulating film; depositing a titanium film to be in contact with the silicon substrate in the contact hole; and causing a heat reaction between the titanium film and the silicon substrate such that the titanium film is subjected to silicide reaction with the thickness 4 nm to 48 nm or, more preferably, with the thickness of 8 nm to 34 nm. In the instance where the contact hole is filled with doped polycrystal silicon material, the titanium film is deposited to be in contact with the polycrystal silicon in the contact hole. The silicon substrate/silicon body may have at least a MISFET formed thereon in which case the contact hole is formed to expose an active region of the MISFET, as one example.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: January 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiromi Todorobaru, Hideo Miura, Masayuki Suzuki, Shinji Nishihara, Shuji Ikeda, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Atushi Ogishima, Hiroyuki Uchiyama, Sonoko Abe
  • Publication number: 20020190295
    Abstract: Bit lines BL of a DRAM that are narrowed to 0.1 &mgr;m or less are made of two-layered conductive films, in which a W (tungsten) film is deposited on a WN (tungsten nitride) film. For bit lines BL, fewer W atoms diffuse across the interface between the W film and the WN film, within crystal grains, and at grain boundaries of the W film, and no tensile stress exists in the W film. Therefore, high-temperature thermal processing in the capacitor formation process does not cause wiring breaks even when the width of the bit lines BL is narrowed to 0.1 &mgr;m or less.
    Type: Application
    Filed: August 1, 2002
    Publication date: December 19, 2002
    Inventors: Masayuki Suzuki, Kentaro Yamada, Masashi Sahara, Takashi Nakajima, Naoki Kanda, Hidenori Suzuki, Yoshinori Matsumuro
  • Publication number: 20020167091
    Abstract: There is provided a semiconductor device having high reliability, high yield, and such a interconnection structure as short hardly occurs. The semiconductor device comprises a semiconductor substrate, metal conductors formed on a side of a main face of the substrate which metal conductors contain aluminum as main constituent thereof and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.
    Type: Application
    Filed: July 1, 2002
    Publication date: November 14, 2002
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Patent number: 6476492
    Abstract: In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hideo Miura, Takashi Nakajima, Hiroyuki Ohta, Shinji Nishihara, Masashi Sahara
  • Patent number: 6472754
    Abstract: The object of the invention is to provide such a highly reliable semiconductor device as no defect such as the breakage of a tungsten conductor occurs. This object is achieved by the following means, i.e., a molybdenum film, a tungsten film and another molybdenum film are deposited in this order on an interlayer dielectric film formed on a silicon substrate.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: October 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Nakajima, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Shinji Nishihara, Masashi Sahara, Kentaro Yamada, Masayuki Suzuki
  • Publication number: 20020115281
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Application
    Filed: December 3, 2001
    Publication date: August 22, 2002
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Patent number: 6429476
    Abstract: Bit lines BL of a DRAM that are narrowed to 0.1 &mgr;m or less are made of two-layered conductive films, in which a W (tungsten) film is deposited on a WN (tungsten nitride) film. For bit lines BL, fewer W atoms diffuse across the interface between the W film and the WN film, within crystal grains, and at grain boundaries of the W film, and no tensile stress exists in the W film. Therefore, high-temperature thermal processing in the capacitor formation process does not cause wiring breaks even when the width of the bit lines BL is narrowed to 0.1 &mgr;m or less.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: August 6, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Suzuki, Kentaro Yamada, Masashi Sahara, Takashi Nakajima, Naoki Kanda, Hidenori Suzuki, Yoshinori Matsumuro
  • Publication number: 20020048947
    Abstract: To provide a high-performance semiconductor integrated circuit in which the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM.
    Type: Application
    Filed: October 12, 2001
    Publication date: April 25, 2002
    Inventors: Masashi Sahara, Fumiaki Endo, Masanori Kojima, Katsuhiro Uchimura, Hideaki Kanazawa, Masakazu Sugiura
  • Publication number: 20020036350
    Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 28, 2002
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hideo Miura, Shinji Nishihara, Masashi Sahara
  • Publication number: 20020024140
    Abstract: The object of the invention is to provide such a highly reliable semiconductor device as no defect such as the breakage of a tungsten conductor occurs. This object is achieved by the following means, i.e., a molybdenum film, a tungsten film and another molybdenum film are deposited in this order on an interlayer dielectric film formed on a silicon substrate.
    Type: Application
    Filed: April 2, 2001
    Publication date: February 28, 2002
    Inventors: Takashi Nakajima, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Shinji Nishihara, Masashi Sahara, Kentaro Yamada, Masayuki Suzuki
  • Publication number: 20020019124
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Application
    Filed: August 21, 2001
    Publication date: February 14, 2002
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Publication number: 20010050386
    Abstract: Bit lines BL of the DRAM that are narrowed to 0.1 &mgr;m or less are made of two-layered conductive films, in which a W (tungsten) film is deposited on a WN (tungsten nitride) film. For bit lines BL, fewer W atoms diffuse across the interface between the W film and the WN film, within crystal grains, and at grain boundaries of the W film, and no tensile stress exists in the W film. Therefore, high-temperature thermal processing in the capacitor formation process does not cause wiring breaks even when the width of bit lines BL is narrowed to 0.1 &mgr;m or less.
    Type: Application
    Filed: March 1, 2001
    Publication date: December 13, 2001
    Inventors: Masayuki Suzuki, Kentaro Yamada, Masashi Sahara, Takashi Nakajima, Naoki Kanda, Hidenori Suzuki, Yoshinori Matsumuro
  • Patent number: 6300237
    Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminium film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: October 9, 2001
    Assignees: Hitachi Ltd., Hitachi ULSI Engineering Corp., Hitachi Microcomputer System Ltd.
    Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
  • Publication number: 20010023958
    Abstract: A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm, or preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.
    Type: Application
    Filed: January 23, 2001
    Publication date: September 27, 2001
    Inventors: Hiromi Todorobaru, Hideo Miura, Masayuki Suzuki, Shinji Nishihara, Shuji Ikeda, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Atushi Ogishima, Hiroyuki Uchiyama, Sonoko Abe