Abstract: Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors.

Abstract: To provide a uniform-type platinum-loaded alumina catalyst demonstrating excellent performance in terms of catalyst life, a uniform-type platinum-loaded alumina catalyst includes: an alumina carrier; sulfur or a sulfur compound dispersed over an entire cross section of the alumina carrier; platinum dispersed and loaded over the entire cross section of the alumina carrier; one or more alkali metals selected from the group consisting of sodium, potassium, and calcium. Preferably, the content of platinum is 0.05 to 5.0 wt % calculated as elemental platinum. The content of the sulfur or the sulfur compound preferably is 0.15 to 5.0 wt % calculated as elemental sulfur. The content of the alkali metal preferably is 0.1 to 5.0 wt % calculated as elemental alkali metal.

Abstract: To provide an egg shell-type platinum-loaded alumina catalyst demonstrating excellent performance in terms of catalyst life, an egg shell-type platinum-loaded alumina catalyst includes: an alumina carrier; platinum dispersed and loaded on an outer shell of the alumina carrier; and one or more second components selected from the group consisting of vanadium, chromium, molybdenum, and phosphorus. Preferably, the content of platinum is 0.05 to 5.0 wt % calculated as elemental platinum. The content of each second component preferably is 0.1 to 5.0 wt % calculated as each element. The alumina carrier has a surface area of 150 m2/g or more, a pore volume of 0.40 cm3/g or more, and an average pore diameter of 40 to 300 ?, with pores having a pore diameter in a range of ±30 ? from the average pore diameter occupying 60% or more of a total pore volume.

Abstract: There is provided a time measuring device including: a first counter unit (204) that acquires a difference time between a first measured signal and a second measured signal as a first measurement result by counting on the basis of a reference clock signal; a delay signal generation unit (208) that generates a delay signal by delaying the first measured signal on the basis of the first measurement result fed back from the first counter unit; a measurement unit (210) that measures a difference time between the delay signal and the second measured signal as a second measurement result; and an operation unit (212) that performs an operation by using the first measurement result and the second measurement result.

Abstract: An imaging element includes: a pixel board including a light receiver including plural pixels, each pixel being configured to generate an imaging signal; a circuit board including a functional circuit, the pixel board being layered on the circuit board; plural wiring portions configured to electrically connect the pixel board and the circuit board to each other and electrically transmit signals between respective layers; a terminal provided on the circuit board, the terminal being electrically connected to each of the plural wiring portions, the terminal being configured to output the imaging signal to an outside of the terminal or receive an external signal from the outside of the terminal; and a switch configured to output, by selective switching, at least one of the imaging signal and an internal signal generated at the circuit board, to the terminal.

Abstract: An endoscope includes: an image sensor having a light receiving plane; a laminate provided to be opposed to an opposite side of the image sensor from the light receiving plane and having a plurality of layers formed by lamination of a plurality of semiconductor elements; and an insertion section having the image sensor and the laminate therein. The laminate includes: a first active layer in which a first active element is provided; a first passive layer in which a first passive element is provided and which is provided between the first active layer and the image sensor; and a through-silicon via provided in each of the first active layer and the first passive layer.

Abstract: To provide an electronic control device capable of securing electromagnetic compatibility and mechanical strength. An electronic control device includes a base portion formed in a bottomed cylindrical shape; an electronic control board provided in the base portion; and connectors provided on an opening side of the base portion and electrically connected to the electronic control board, in which the base portion includes a first layer formed of a conductive member and a second layer formed of a member different from that of the first layer.

Abstract: Provided is a gateway device capable of reducing power consumption in a sleep state and relaying an activation signal between networks without delay. When receiving an activation signal, the gateway device according to the present invention transfers the activation signal to another network via a relay switch, and outputs a signal indicating the reception of the activation signal from a transceiver, thereby turning on a microcomputer.

Abstract: A plasma processing apparatus includes a process container that forms a process space to accommodate a target substrate, and a first electrode and a second electrode disposed opposite each other inside the process container. The first electrode is an upper electrode and the second electrode is a lower electrode and configured to support the target substrate through a mount face. A correction ring is disposed to surround the target substrate placed on the mount face of the second electrode. The correction ring includes a combination of a first ring to be around the target substrate and a second ring arranged around or above the first ring. A power supply unit is configured to apply a first electric potential and a second electric potential respectively to the first ring and the second ring to generate a potential difference between the first and second rings. The power supply unit is configured to variably set the potential difference.

Abstract: In an imaging system, a differential signal transmission circuit is configured to output a first signal to a first signal line in an image output period and is configured to output a second signal to a second signal line in the image output period. The first signal and the second signal are included in a differential signal. A signal output circuit is configured to output a second clock signal to the first signal line in a blanking period different from the image output period and is configured to output a second control signal to the second signal line in the blanking period. In a PLL, connection between a charge pump and a loop filter is controlled on the basis of the second control signal output to the second signal line.

Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.

Abstract: A plasma processing apparatus includes: an evacuable processing chamber including a dielectric window; a substrate supporting unit, provided in the processing chamber, for mounting thereon a target substrate; a processing gas supply unit for supplying a desired processing gas to the processing chamber to perform a plasma process on the target substrate; a first RF antenna, provided on the dielectric window, for generating a plasma by an inductive coupling in the processing chamber; and a first RF power supply unit for supplying an RF power to the first RF antenna. The first RF antenna includes a primary coil provided on or above the dielectric window and electrically connected to the first RF power supply unit; and a secondary coil provided such that the coils are coupled with each other by an electromagnetic induction therebetween while being arranged closer to a bottom surface of the dielectric window than the primary coil.

Abstract: A plasma processing apparatus includes a processing chamber including a dielectric window; a coil shaped RF antenna provided outside the dielectric window; a substrate supporting unit, provided in the processing chamber, for mounting thereon a target substrate to be processed; a processing gas supply unit for supplying a desired processing gas to the processing chamber to perform a desired plasma process on the target substrate; and an RF power supply unit for supplying an RF power to the RF antenna to generate a plasma of the processing gas by an inductive coupling in the processing chamber. The apparatus further includes a floating coil electrically floated and arranged at a position outside the processing chamber where the floating coil is to be coupled with the RF antenna by an electromagnetic induction; and a capacitor provided in a loop of the floating coil.

Abstract: Provided is a gateway device capable of reducing power consumption in a sleep state and relaying an activation signal between networks without delay. When receiving an activation signal, the gateway device according to the present invention transfers the activation signal to another network via a relay switch, and outputs a signal indicating the reception of the activation signal from a transceiver, thereby turning on a microcomputer.

Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.

Abstract: According to the present disclosure, a photoelectric conversion film includes a plurality of semiconductor nanoparticles and a matrix phase provided around each of the plurality of semiconductor nanoparticles. The matrix phase includes a principal phase including a composite, which includes an organic molecule polymer and an inorganic material. A photoelectric conversion device includes a transparent electrically conductive film, a photoelectric conversion layer, a semiconductor substrate, and an electrode layer, which are layered on a glass substrate in this order. The photoelectric conversion layer includes the photoelectric conversion film.

Abstract: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.

Abstract: An imaging element includes: a pixel chip where a pixel unit and a vertical selecting unit are arranged, the pixel unit including plural pixels that are arranged in a two-dimensional matrix, the pixels being configured to generate and output imaging signals; a transmission chip where at least a power source unit and a transmission unit are arranged; plural capacitative chips, each capacitative chip having capacitance functioning as a bypass condenser for a power source in the power source unit; and plural connecting portions configured to electrically connect the pixel chip, the transmission chip, and the capacitative chip respectively to another chip. The transmission chip is layered and connected at a back surface side of the pixel chip. The capacitative chips are layered and connected at a back surface side of the transmission chip. The connecting portions are arranged so as to overlap one another.

Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.

Abstract: An imaging device includes: a first chip including a light receiving unit, and a read circuit; a second chip including a timing control circuit, an A/D conversion circuit, and a cable transmission circuit; and a connection unit configured to connect the first and the second chips. The read circuit includes a column read circuit and a horizontal selection circuit, and a vertical selection circuit. The connection unit of the first chip is provided in a first area along a side of the rectangular light receiving unit, and in a second area adjacent to the column read circuit, the horizontal selection circuit, and the vertical selection circuit. The connection unit of the second chip is provided in a third area around the timing control circuit, the A/D conversion circuit, and the cable transmission circuit and in a fourth area adjacent to the timing control circuit and the A/D conversion circuit.