Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “1” (or logic “1) is successively performed.

Abstract: The semiconductor memory device of the present invention is provided with a switching element comprised of a single channel MOS transistor at a halfway of a path used to transmit a high voltage supplied to the memory array via the external terminal at the time of a test performance, so that the switching element is turned off when a word line is changed to another, thereby resetting of the supply voltage having been required conventionally for each test performance is omitted.

Abstract: A nonvolatile semiconductor memory device includes a memory array which comprises a plurality of memory cells of a type wherein predetermined voltages are applied to selected memory cells to change their threshold voltages, whereby information are stored therein according to the difference between the threshold voltages, and whose some memory cells are used as spare memory cells. The nonvolatile semiconductor memory device is provided with a latch circuit connected to each bit line of the memory array through a transmission switch. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

Abstract: Aluminum hydroxide aggregated particles which have an average particle diameter of not less than 40 &mgr;m, an average particle diameter as determined after pressing at 1,000 kg/cm2 of not more than 35 &mgr;m, and an L value of slurry obtained by mixing 20 ml of glycerol and 10 g of the aluminum hydroxide aggregated particles of not more than 69, are obtained by a process comprising the steps of:

Abstract: The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section 16 and the detection voltage obtained by dividing a supply voltage VCC by means of resistors 27 and 28 and outputs it as a detection signal K. The reference voltage generating section 16 generates reference voltage VREF from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage VCC can be minimized.

Abstract: A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.

Abstract: The semiconductor memory device of the present invention is provided with a switching element comprised of a single channel MOS transistor at a halfway of a path used to transmit a high voltage supplied to the memory array via the external terminal at the time of a test performance, so that the switching element is turned off when a word line is changed to another, thereby resetting of the supply voltage having been required conventionally for each test performance is omitted.

Abstract: Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management.

Abstract: A nonvolatile semiconductor memory device includes a memory array which comprises a plurality of memory cells of a type wherein predetermined voltages are applied to selected memory cells to change their threshold voltages, whereby information are stored therein according to the difference between the threshold voltages, and whose some memory cells are used as spare memory cells. The nonvolatile semiconductor memory device is provided with a latch circuit connected to each bit line of the memory array through a transmission switch. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.

Abstract: A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation.

Abstract: A nonvolatile semiconductor memory device includes a memory array which comprises a plurality of memory cells of a type wherein predetermined voltages are applied to selected memory cells to change their threshold voltages, whereby information are stored therein according to the difference between the threshold voltages, and whose some memory cells are used as spare memory cells. The nonvolatile semiconductor memory device is provided with a latch circuit connected to each bit line of the memory array through a transmission switch. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

Abstract: A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation.

Abstract: A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data-input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation.

Abstract: A semiconductor memory (1), having a plurality of memory blocks (2 and 3) provided with a plurality of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating defective memory blocks and detection means (32) for detecting an access to a defective memory block designated by the first storage means in accordance with an address signal. When the detection means detects an access to a defective memory, the first control means inhibits the data rewrite operation for an instruction for a data rewrite operation and inhibits the output of data from the input/output buffer for the data read operation.

Abstract: A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvo

Abstract: It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.

Abstract: Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.

Abstract: The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.