Abstract: A memory area within a semiconductor integrated circuit device is accessible through an address changeover circuit. External control signals instruct the memory device as to the addressing mode desired. Address signals originating externally are provided directly to the IC's address decoder circuits, while addresses originating internal to the IC are first shifted one or two bits to modify the address by a power of 2, then provided to the address decoder circuits. In this way, data of bit length N may be written to a memory array of bit length M, where M>N.

Abstract: An integrated circuit device for writing and reading information comprising an array of plural non-volatile memory elements of insulated-gate field effect type formed on a semiconductor substrate of one conductivity type; plural sets of two complementary insulated-gate type field effect transistors of P-channel type and N-channel type formed on the substrate, which transistors constitute a control circuit for the memory elements; and a latch-up suppressant, comprising a long and narrow semiconductor region of the one conductivity type which has an impurity concentration higher than that of the substrate and is formed between the array and the control circuit in a surface region of the substrate, with a predetermined voltage applied directly to the semiconductor region.

Abstract: A semiconductor memory device and a method for manufacturing such a device provides increased capacitance for memory cells of a dynamic RAM by using the top and sides of island regions formed in the substrate.

Abstract: A nonvolatile semiconductor memory device has a memory cell array including a MOS FET with a floating gate, first and second control gates and a program electrode; column and row decoders for selecting a specific memory cell; a program control circuit for programming data on the floating gate; and a timing circuit for providing operation timings of the column and row decoders and the program control circuit. The timing circuit sets up a program inhibit period ranging over time point at which a selected memory cell is to be erased and programmed. In the program inhibit period, one of the first and second control gates of each of the memory cells is at a high potential, while the other control gate is at low potential.

Abstract: In an electrically erasable and programmable read only memory of this invention, each memory cell has an L-shaped floating gate insulated from a substrate. The floating gate and a first control gate, the floating gate and a second control gate, and the floating gate and a source electrode connected to a source are capacitively coupled at predetermined capacitances, respectively. A projecting portion which is formed in the source electrode underlies a coupling region of first and second gate portions of the floating gate. When a voltage of +20 V is applied to the source electrode and a voltage of 0 V is applied to the first and second gates, electrons stored in the floating gate of at least one desired memory cell may be discharged.