Abstract: In an electrically erasable and programmable read only memory of this invention, each memory cell has an L-shaped floating gate insulated from a substrate. The floating gate and a first control gate, the floating gate and a second control gate, and the floating gate and a source electrode connected to a source are capacitively coupled at predetermined capacitances, respectively. A projecting portion which is formed in the source electrode underlies a coupling region of first and second gate portions of the floating gate. When a voltage of +20 V is applied to the source electrode and a voltage of 0 V is applied to the first and second gates, electrons stored in the floating gate of at least one desired memory cell may be discharged.