Patents by Inventor Masato Koyama

Masato Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060186488
    Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.
    Type: Application
    Filed: April 20, 2006
    Publication date: August 24, 2006
    Inventors: Masahiro Koike, Masato Koyama, Tsunehiro Ino, Yuuichi Kamimuta, Akira Takashima, Masamichi Suzuki, Akira Nishiyama
  • Publication number: 20060186489
    Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.
    Type: Application
    Filed: April 20, 2006
    Publication date: August 24, 2006
    Inventors: Masahiro Koike, Masato Koyama, Tsunehiro Ino, Yuuichi Kamimuta, Akira Takashima, Masamichi Suzuki, Akira Nishiyama
  • Publication number: 20060180870
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Application
    Filed: December 13, 2005
    Publication date: August 17, 2006
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Patent number: 7087969
    Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Nishiyama, Mizuki Ono, Masato Koyama, Takamitsu Ishihara
  • Patent number: 7078330
    Abstract: A metal electrode is formed on a substrate. The metal electrode includes a first layer, a second layer, and a third layer lying, from an outermost surface of the metal electrode toward the substrate, in this order. The first layer contains tin as a principal constituent and the second layer contains a metallic element which produces an eutectic reaction with tin, wherein the melting point of the first layer is higher than the melting point of the second layer. The third layer is an underlying metallic layer for the first and second layers.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: July 18, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Maeda, Takeyuki Maegawa, Shigeru Matsuno, Takuo Ozawa, Takanori Sone, Shoji Miyashita, Yasumichi Hatanaka, Masato Koyama, Takahiro Nagamine, Susumu Arai
  • Patent number: 7075158
    Abstract: A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: July 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Akira Nishiyama, Masamichi Suzuki, Yuuichi Kamimuta, Tsunehiro Ino
  • Publication number: 20060138554
    Abstract: The present invention is intended to provide a semiconductor device having a gate electrode free from increasing of resistance of the gate electrode, from decreasing of capacitance of the insulation film due to depletion, and from penetrating of impurity. The semiconductor device comprises a silicon layer, a gate insulating film formed on the silicon layer, a metal boron compound layer formed on the gate insulating film, and a gate electrode formed on the metal boron compound layer and containing at least silicon.
    Type: Application
    Filed: January 27, 2006
    Publication date: June 29, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Akira Nishiyama
  • Patent number: 7053455
    Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Koike, Masato Koyama, Tsunehiro Ino, Yuuichi Kamimuta, Akira Takashima, Masamichi Suzuki, Akira Nishiyama
  • Publication number: 20060027879
    Abstract: A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.
    Type: Application
    Filed: October 6, 2005
    Publication date: February 9, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Akira Nishiyama, Masamichi Suzuki, Yuuichi Kamimuta, Tsunehiro Ino
  • Patent number: 6982467
    Abstract: A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: January 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Akira Nishiyama, Masamichi Suzuki, Yuuichi Kamimuta, Tsunehiro Ino
  • Publication number: 20050184346
    Abstract: A semiconductor device includes a silicon substrate, a channel region formed in a surface of the silicon substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, first gate side walls formed on the gate insulating film to sandwich the gate electrode in a gate length direction, second gate side walls which sandwich the gate electrode and the first gate side wall, first diffused layers formed on the surface of the silicon substrate to sandwich the channel region, second diffused layers which sandwich the channel region and the first diffused layer and have a larger depth than that of the first diffused layer, and low resistance layers which are formed between the first diffused layer and the second gate side wall and contain nitride, boride or carbide of Ti, Zr, Hf or Ta.
    Type: Application
    Filed: February 8, 2005
    Publication date: August 25, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masato Koyama, Akira Nishiyama, Yuuichi Kamimuta
  • Patent number: 6864663
    Abstract: An object of the invention is to maintain high vehicle driving performance and system efficiency by preventing reductions in the traction characteristic and the maximum driving speed of a vehicle. The invention relates to an electrical system for an electric automotive vehicle for driving the vehicle by supplying an electric power of a direct-current power supply to an electric motor for driving wheels via a semiconductor power converter for driving the wheels such as an inverter and speed-variably driving this electric motor or an electrical system for an electric automotive vehicle using an engine and a direct-current power supply as driving sources. A booster chopper 200 is connected between a battery device 1 or 4 as the direct-current power supply and an inverter 2 or a semiconductor power converter 100, and is controlled so that a direct-current input voltage of the inverter 2 or the like becomes substantially constant.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: March 8, 2005
    Assignees: Kobelco Construction Machinery Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayuki Komiyama, Toshio Sora, Masato Koyama, Michio Kataoka
  • Patent number: 6849908
    Abstract: A good interface characteristic can be maintained, and a leakage current of a dielectric film can be decreased. A semiconductor device according to one aspect of the present invention includes: a semiconductor substrate; a gate dielectric film containing at least nitrogen and a metal, the gate dielectric film being formed on the semiconductor substrate, and including a first layer region contacting the semiconductor substrate, a second layer region located at a side opposite to that of the first layer region in the gate dielectric film, and a third layer region located between the first and second layer regions, a maximum value of a nitrogen concentration in the third layer region being higher than maximum values thereof in the first and second layer regions; a gate electrode contacting the second layer region; and a pair of source and drain regions formed at both sides of the gate dielectric film in the semiconductor substrate.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: February 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Masato Koyama, Akira Nishiyama
  • Publication number: 20050017305
    Abstract: A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.
    Type: Application
    Filed: June 9, 2004
    Publication date: January 27, 2005
    Inventors: Masato Koyama, Akira Nishiyama, Masamichi Suzuki, Yuuichi Kamimuta, Tsunehiro Ino
  • Publication number: 20040207023
    Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.
    Type: Application
    Filed: January 21, 2004
    Publication date: October 21, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Nishiyama, Mizuki Ono, Masato Koyama, Takamitsu Ishihara
  • Patent number: 6803635
    Abstract: There is disclosed a MIS field effect transistor, comprising a silicon substrate, an insulating film formed over the silicon substrate and containing silicon and at least one of nitrogen and oxygen, a metal oxynitride film formed on the insulating film and containing at least one kind of metal atom selected from the group consisting of zirconium, hafnium and a lanthanoide series metal, the metal oxynitride film containing nitrogen atom not bonding with the metal atom without metal-nitrogen bond at the density of higher than 1019/cm3, and a gate electrode formed on the metal oxynitride film.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: October 12, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Akira Nishiyama
  • Publication number: 20040178480
    Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed on the surface of the substrate, and an electrode formed on the insulating film. The substrate side of the insulating film is formed of an epitaxial crystalline insulating layer containing metal, silicon and oxygen, and the electrode side of the insulating film is formed of an amorphous insulating layer additionally containing nitrogen.
    Type: Application
    Filed: December 4, 2003
    Publication date: September 16, 2004
    Inventors: Masato Koyama, Akira Nishiyama
  • Publication number: 20040175917
    Abstract: A metal electrode of the invention is formed on a substrate. The metal electrode includes a first layer, a second layer and a third layer lying from an outermost surface of the metal electrode toward the substrate in this order. The first layer contains tin as a principal constituent and the second layer contains a metallic element which produces an eutectic reaction with tin, wherein the melting point of the first layer is higher than that of the second layer. The third layer is formed as an underlying metallic layer for the first and second layers.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 9, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Maeda, Takeyuki Maegawa, Shigeru Matsuno, Takuo Ozawa, Takanori Sone, Shoji Miyashita, Yasumichi Hatanaka, Masato Koyama, Takahiro Nagamine, Susumu Arai
  • Publication number: 20040169240
    Abstract: A semiconductor device comprises a substrate and a MISFET including source-drain regions formed in the substrate and a gate electrode formed on the substrate with a gate insulating film interposed therebetween. The gate electrode is formed of a metal oxynitride film containing a metal-oxygen-nitrogen bond chain. Alternatively, the gate insulating film is formed of a nitrided metal silicate film containing at least one of a metal-oxygen-nitrogen bond chain and asilicon-oxygen-nitrogen bond chain.
    Type: Application
    Filed: December 4, 2003
    Publication date: September 2, 2004
    Inventors: Masato Koyama, Akira Nishiyama, Yasushi Nakasaki, Masamichi Suzuki, Yuuichi Kamimuta, Akio Kaneko
  • Publication number: 20040164329
    Abstract: A good interface characteristic can be maintained, and a leakage current of a dielectric film can be decreased. A semiconductor device according to one aspect of the present invention includes: a semiconductor substrate; a gate dielectric film containing at least nitrogen and a metal, the gate dielectric film being formed on the semiconductor substrate, and including a first layer region contacting the semiconductor substrate, a second layer region located at a side opposite to that of the first layer region in the gate dielectric film, and a third layer region located between the first and second layer regions, a maximum value of a nitrogen concentration in the third layer region being higher than maximum values thereof in the first and second layer regions; a gate electrode contacting the second layer region; and a pair of source and drain regions formed at both sides of the gate dielectric film in the semiconductor substrate.
    Type: Application
    Filed: February 6, 2004
    Publication date: August 26, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Izumi Hirano, Masato Koyama, Akira Nishiyama