Patents by Inventor Masato Yoshida

Masato Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140076396
    Abstract: The semiconductor substrate of the present invention contains a semiconductor layer and an impurity diffusion layer containing at least one impurity atom selected from the group consisting of an n-type impurity atom and a p-type impurity atom and at least one metallic atom selected from the group consisting of K, Na, Li, Ba, Sr, Ca, Mg, Be, Zn, Pb, Cd, V, Sn, Zr, Mo, La, Nb, Ta, Y, Ti, Ge, Te, and Lu.
    Type: Application
    Filed: November 24, 2013
    Publication date: March 20, 2014
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Tetsuya SATO, Masato YOSHIDA, Takeshi NOJIRI, Yoichi MACHII, Mitsunori IWAMURO, Akihiro ORITA
  • Publication number: 20140065761
    Abstract: The composition for forming a composition for forming a p-type diffusion layer, the composition containing a glass powder and a dispersion medium, in which the glass powder includes an acceptor element and a total amount of a life time killer element in the glass powder is 1000 ppm or less. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: November 9, 2013
    Publication date: March 6, 2014
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Yoichi MACHII, Masato YOSHIDA, Takeshi NOJIRI, Kaoru OKANIWA, Mitsunori IWAMURO, Shuichiro ADACHI, Tetsuya SATO, Keiko KIZAWA
  • Publication number: 20140060385
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a donor element-containing glass powder and a dispersion medium. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: November 5, 2013
    Publication date: March 6, 2014
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Youichi MACHII, Masato YOSHIDA, Takeshi NOJIRI, Kaoru OKANIWA, Mitsunori IWAMURO, Shuuichirou ADACHI, Takuya Aoyagi
  • Patent number: 8616936
    Abstract: To polish polishing target surfaces of SiO2 insulating films or the like at a high rate without scratching the surface, the present invention provides an abrasive comprising a slurry comprising a medium and dispersed therein at least one of i) cerium oxide particles constituted of at least two crystallites and having crystal grain boundaries or having a bulk density of not higher than 6.5 g/cm3 and ii) abrasive grains having pores. Also provided are a method of polishing a target member and a process for producing a semiconductor which make use of this abrasive.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: December 31, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Masato Yoshida, Toranosuke Ashizawa, Hiroki Terazaki, Yuuto Ootuki, Yasushi Kurata, Jun Matsuzawa, Kiyohito Tanno
  • Publication number: 20130292893
    Abstract: The present invention addresses the issue of providing a jig for fixing a cylinder block, said jig being capable of stably fixing a cylinder block and contributing to a reduction of the size of the whole equipment including a processing tool. A jig for fixing a cylinder block of the present invention is used for the purpose of fixing a cylinder block, and is provided with a table having the cylinder block placed thereon such that the crank cases of the cylinder block are positioned on the lower side, and a clamping device, which can project upward from the upper surface of the table, and which clamps a journal wall that separates the crank cases of the cylinder block from each other.
    Type: Application
    Filed: November 22, 2010
    Publication date: November 7, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masato Yoshida
  • Patent number: 8481569
    Abstract: The present invention aims to provide an iminopyridine derivative compound having an ?1Dadrenergic receptor antagonistic action, which is useful as an agent for the prophylaxis or treatment of a lower urinary tract disease and the like. The present invention provides a compound represented by the formula wherein each symbol is as defined in the specification, or a salt thereof.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: July 9, 2013
    Assignee: Takeda Pharmaceutical Company Limited
    Inventors: Masato Yoshida, Nobuki Sakauchi, Ayumu Sato
  • Patent number: 8470859
    Abstract: Provided are an iminopyridine derivative having a selective ?1D adrenergic receptor antagonistic action and useful as an agent for the prophylaxis or treatment of a lower urinary tract disease and the like, and a screening method for a compound having an ?1D adrenergic receptor antagonistic action. An ?1D adrenergic receptor antagonist containing a compound represented by the formula: wherein each symbol is as defined in the specification, or a salt thereof, and a method of screening for an agent having an ?1D adrenergic receptor antagonistic action for the prophylaxis or treatment of a lower urinary tract disease, which includes measuring the bladder smooth muscle tension of rats with bladder outlet obstruction.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: June 25, 2013
    Assignee: Takeda Pharmaceutical Company Limited
    Inventors: Masato Yoshida, Tomohiko Suzaki, Yasuhisa Kohara, Haruhiko Kuno, Hiroshi Nagabukuro, Reiko Saikawa, Yuuichi Okabe, Shigemitsu Imai
  • Patent number: 8410000
    Abstract: The method for producing a photovoltaic cell includes applying, on a partial region of one surface side of a semiconductor substrate, a first p-type diffusion layer forming composition including a p-type impurity-containing glass powder and a dispersion medium; applying, on at least a region other than the partial region on the surface of the semiconductor substrate, a second p-type diffusion layer forming composition which includes a p-type impurity-containing glass powder and a dispersion medium and in which a concentration of the p-type impurity is lower than that of the first p-type diffusion layer forming composition, where the first p-type diffusion layer forming composition is applied; heat-treating the semiconductor substrate on which the first p-type diffusion layer forming composition and the second p-type diffusion layer forming composition are applied to form a p-type diffusion layer; and forming an electrode on the partial region.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: April 2, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Youichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Akihiro Orita, Tetsuya Satou, Keiko Kizawa
  • Publication number: 20130078759
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a glass powder and a dispersion medium, in which the glass powder includes an donor element and a total amount of the life time killer element in the glass powder is 1000 ppm or less. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: April 22, 2011
    Publication date: March 28, 2013
    Inventors: Yoichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuichiro Adachi, Tetsuya Sato, Keiko Kizawa
  • Patent number: 8404599
    Abstract: The method for producing a photovoltaic cell includes applying, on a partial region of one surface side of a semiconductor substrate, a first n-type diffusion layer forming composition including an n-type impurity-containing glass powder and a dispersion medium; applying, on at least a region other than the partial region on the surface of the semiconductor substrate, a second n-type diffusion layer forming composition which includes an n-type impurity-containing glass powder and a dispersion medium and in which a concentration of the n-type impurity is lower than that of the first n-type diffusion layer forming composition, where the first n-type diffusion layer forming composition is applied; heat-treating the semiconductor substrate on which the first n-type diffusion layer forming composition and the second n-type diffusion layer forming composition are applied to form an n-type diffusion layer; and forming an electrode on the partial region.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: March 26, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Youichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Akihiro Orita, Tetsuya Satou, Keiko Kizawa
  • Publication number: 20130071968
    Abstract: The composition for forming a composition for forming a p-type diffusion layer, the composition containing a glass powder and a dispersion medium, in which the glass powder includes an acceptor element and a total amount of a life time killer element in the glass powder is 1000 ppm or less. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: April 22, 2011
    Publication date: March 21, 2013
    Inventors: Yoichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuichiro Adachi, Tetsuya Sato, Keiko Kizawa
  • Publication number: 20130063913
    Abstract: In a power source control circuit module, switching regulator devices and a linear regulator device are mounted on a surface of a laminated body so as to be spaced from each other. In an interface between dielectric layers of the laminated body, first to fifth internal ground electrodes separated by an electrode non-formation portion are provided. The first, second, fourth, and fifth internal ground electrode are connected to the respective switching regulator devices. The third internal ground electrode is connected to the linear regulator device. The first to fifth internal ground electrodes are connected to respective different external ground terminals.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 14, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Masato YOSHIDA, Tomohiro NAGAI, Hiroshi MATSUBARA
  • Publication number: 20130063902
    Abstract: A power supply control IC is mounted on a surface of a multilayer body that defines a power supply control circuit module. A first inner-layer electrode connecting an inductor element and a switching regulator element for the power supply control IC, another first inner-layer electrode connecting the inductor element and a capacitor element, and still another first inner-layer electrode connecting the switching regulator element and the capacitor element are located on upper layer regions of the multilayer body and are routed in between a mounting area of the power supply control IC and a peripheral wall of the multilayer body. The first inner-layer electrodes have widths that are wider than those of second inner-layer electrodes which are located near a center region of the multilayer body and transmit control signals.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 14, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Masato YOSHIDA, Tomohiro NAGAI, Hiroshi MATSUBARA
  • Publication number: 20130042912
    Abstract: The solder bonded body according to the present invention contains: an oxide body to be bonded having an oxide layer on the surface thereof; and a solder layer bonded to the oxide layer, which the solder layer is formed by an alloy containing at least two metals selected from the group consisting of tin, copper, silver, bismuth, lead, aluminum, titanium and silicon and having a melting point of lower than 450° C. and has a zinc content of 1% by mass or less.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 21, 2013
    Inventors: Yoshiaki KURIHARA, Masato Yoshida, Takeshi Nojiri, Shuichiro Adachi, Takashiko Kato, Yasushi Kurata
  • Publication number: 20130025668
    Abstract: The invention provides an element including a semiconductor substrate and an electrode disposed on the semiconductor substrate, the electrode being a sintered product of a composition for an electrode that includes phosphorus-containing copper alloy particles, glass particles and a dispersing medium, and the electrode includes a line-shaped electrode having an aspect ratio, which is defined as electrode short length:electrode height, of from 2:1 to 250:1.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Inventors: Shuichiro ADACHI, Masato Yoshida, Takeshi Nojiri, Yoshiaki Kurihara, Takahiko Kato
  • Publication number: 20130025670
    Abstract: The semiconductor substrate of the present invention contains a semiconductor layer and an impurity diffusion layer containing at least one impurity atom selected from the group consisting of an n-type impurity atom and a p-type impurity atom and at least one metallic atom selected from the group consisting of K, Na, Li, Ba, Sr, Ca, Mg, Be, Zn, Pb, Cd, V, Sn, Zr, Mo, La, Nb, Ta, Y, Ti, Ge, Te, and Lu.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Inventors: Tetsuya SATO, Masato YOSHIDA, Takeshi NOJIRI, Yoichi MACHII, Mitsunori IWAMURO, Akihiro ORITA
  • Publication number: 20130025669
    Abstract: The invention provides a photovoltaic cell substrate that is a semiconductor substrate comprising an n-type diffusion layer, an n+-type diffusion layer having a higher n-type impurity concentration than the n-type diffusion layer, and a concave portion at a surface of the n+-type diffusion layer.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Inventors: Tetsuya SATO, Masato Yoshida, Takeshi Nojiri, Youichi Machii, Mitsunori Iwamuro, Akihiro Orita
  • Publication number: 20130026648
    Abstract: Disclosed is a film for forming a semiconductor protection film, which protects a surface of a semiconductor element that is mounted on a structure such as a substrate and is located on the outermost side, the surface being on the reverse side of the surface at which the semiconductor element is mounted on the structure, and the resin composition constituting the film for forming a semiconductor protection film contains (A) a thermosetting component and (B) an inorganic filler.
    Type: Application
    Filed: August 5, 2010
    Publication date: January 31, 2013
    Inventors: Takashi Hirano, Masato Yoshida
  • Publication number: 20130020119
    Abstract: A circuit module includes a substrate that has a substantially rectangular parallelepiped shape and includes a plurality of inner conductive layers, an electronic component disposed on a first main surface of the substrate, an insulating layer disposed on the first main surface of the substrate so as to cover the electronic component, a shielding layer disposed on a surface of the insulating layer, and a ground electrode connected to the plurality of inner conductive layers. At least two of the inner conductive layers are directly connected to the shielding layer.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 24, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Masato YOSHIDA
  • Publication number: 20120313199
    Abstract: The invention provides a material for forming a passivation film for a semiconductor substrate. The material includes a polymer compound having an anionic group or a cationic group.
    Type: Application
    Filed: May 25, 2012
    Publication date: December 13, 2012
    Inventors: Akihiro Orita, Masato Yoshida, Takeshi Nojiri, Yoichi Machii, Mitsunori Iwamuro, Shuchiro Adachi, Tetsuya Sato, Toru Tanaka