Patents by Inventor Masatomi Okanishi

Masatomi Okanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9472563
    Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: October 18, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Masatomi Okanishi
  • Publication number: 20120315750
    Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.
    Type: Application
    Filed: December 12, 2011
    Publication date: December 13, 2012
    Inventor: Masatomi Okanishi
  • Patent number: 8183622
    Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: May 22, 2012
    Assignee: Spansion LLC
    Inventor: Masatomi Okanishi
  • Publication number: 20120083086
    Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 5, 2012
    Inventor: Masatomi OKANISHI
  • Patent number: 8097518
    Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: January 17, 2012
    Assignee: Spansion LLC
    Inventor: Masatomi Okanishi
  • Patent number: 7915661
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: March 29, 2011
    Assignee: Spansion LLC
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Publication number: 20110020996
    Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
    Type: Application
    Filed: October 6, 2010
    Publication date: January 27, 2011
    Inventor: Masatomi OKANISHI
  • Patent number: 7847340
    Abstract: The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions on the semiconductor substrate, the portions being located between the word lines, the silicon oxide layers being located between the trapping layers.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: December 7, 2010
    Assignee: Spansion LLC
    Inventors: Kenichi Fujii, Masatomi Okanishi
  • Patent number: 7825457
    Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 2, 2010
    Assignee: Spansion LLC
    Inventor: Masatomi Okanishi
  • Patent number: 7825448
    Abstract: A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: November 2, 2010
    Assignee: Spansion LLC
    Inventors: Masatomi Okanishi, Yoshihiro Mikasa, Hiroshi Murai
  • Publication number: 20100001333
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor deice and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Application
    Filed: August 18, 2009
    Publication date: January 7, 2010
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Patent number: 7589371
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: September 15, 2009
    Assignee: Spansion LLC
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Publication number: 20090200599
    Abstract: A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.
    Type: Application
    Filed: August 15, 2008
    Publication date: August 13, 2009
    Inventors: Masatomi OKANISHI, Yoshihiro MIKASA, Hiroshi Murai
  • Publication number: 20080191321
    Abstract: The present invention provides a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including: ONO films that are formed on a semiconductor substrate and include trapping layers; word lines that are formed on the ONO films; and silicon oxide layers that are formed at portions on the semiconductor substrate, the portions being located between the word lines, the silicon oxide layers being located between the trapping layers.
    Type: Application
    Filed: December 21, 2007
    Publication date: August 14, 2008
    Applicant: SPANSION LLC
    Inventors: Kenichi FUJII, Masatomi OKANISHI
  • Patent number: 7387936
    Abstract: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The oxide film has first portions related to the bit areas and a second portion that is located between the bit areas and is thicker than the first potions. The first portions serve as tunneling oxide portions, while the second portion allows reduced tunneling.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: June 17, 2008
    Assignee: Spansion LLC
    Inventor: Masatomi Okanishi
  • Publication number: 20080064181
    Abstract: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The oxide film has first portions related to the bit areas and a second portion that is located between the bit areas and is thicker than the first potions. The first portions serve as tunneling oxide portions, while the second portion allows reduced tunneling.
    Type: Application
    Filed: October 23, 2007
    Publication date: March 13, 2008
    Inventor: Masatomi Okanishi
  • Patent number: 7309893
    Abstract: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The oxide film has first portions related to the bit areas and a second portion that is located between the bit areas and is thicker than the first potions. The first portions serve as tunneling oxide portions, while the second portion allows reduced tunneling.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: December 18, 2007
    Assignee: Spansion LLC
    Inventor: Masatomi Okanishi
  • Publication number: 20070105308
    Abstract: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18) and running in a length direction of the trenches (11). According to the present invention, it is possible to provide a semiconductor deice and a fabrication method therefor, in which higher memory capacity can be achieved.
    Type: Application
    Filed: August 30, 2006
    Publication date: May 10, 2007
    Inventors: Masaya Hosaka, Masatomi Okanishi
  • Publication number: 20070052017
    Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
    Type: Application
    Filed: April 27, 2006
    Publication date: March 8, 2007
    Inventor: Masatomi Okanishi
  • Publication number: 20070026604
    Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 1, 2007
    Inventor: Masatomi Okanishi