SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
This application is a Divisional of U.S. patent application Ser. No. 12/898,968, filed Oct. 6, 2010, which is a Divisional of U.S. patent application Ser. No. 11/414,646, filed Apr. 27, 2006, which is a continuation of International Application No. PCT/JP2005/008057, filed Apr. 27, 2005, which was not published in English under PCT Article 21(2), and are all herein incorporated by reference.
TECHNICAL FIELDThe present invention relates to a semiconductor device and a manufacturing method therefor. In particular, the present invention relates to a semiconductor device having a bit line that serves as a source region and a drain region and is buried in a semiconductor substrate.
BACKGROUNDIn recent years, non-volatile memory semiconductor devices wherein data can be overwritten are widely used. In the technical field of such non-volatile memories, technological developments are being made to miniaturize memory cells for high storage capacity. For example, there are metal oxide nitride oxide silicon (MONOS)-type Flash memories and silicon oxide nitride oxide silicon (SONOS)-type Flash memories in which electric charge is stored in an (ONO) film. Furthermore, flash memories have been developed that have two or more charge storage regions in one transistor for the purpose of increasing storage capacity. For example, U.S. Pat. No. 6,011,725 discloses a transistor having two charge storage regions between a gate electrode and a semiconductor substrate. This transistor interchanges the source and drain and is symmetrically operated. In this manner, a structure that does not differentiate between the source and the drain region may be provided. Furthermore, bit lines serve as the source and drain regions and are buried in the semiconductor substrate. In this way, the memory cells can be miniaturized.
A conventional manufacturing method is explained referring to
In
The semiconductor substrate 10 between the bit lines 30a functions as a channel, electric charge is stored in the ONO film between the channel and the word line 32, and this flash memory functions as a non-volatile memory. The storage of electric charge in the ONO film 18 is performed by applying a high field between the source region and the drain region (namely, between the bit lines 30a), and implanting electrons that have become high energy into the trap layer 14 within the ONO film 18. In addition, favorable writing characteristics can be obtained because the electric field near the high concentration diffusion region 22 on the surface of the semiconductor substrate 10 can be enlarged by the performance of pocket implantation.
In addition, data is erased by applying a negative voltage to the gate electrode (namely, word line 32) and generating Fowler-Nordheim (F-N) tunneling or Band to Band Tunneling current in the tunnel oxide film 12. The charge storage regions can be formed in two locations between the bit lines 30a under the word line 32, by interchanging the source region and the drain region with each other.
Because the bit line 30a is formed from the diffusion region, the resistance 35 thereof is higher than the resistance of metal. As a result, the programming and erasing characteristics become poor. Therefore, the bit line 30a is connected to the wiring layer 36 by contact holes formed on the interlayer insulating film 34 every time a plurality of word lines 32 is crossed. In order to miniaturize the memory cells, the bit line 30a is required to have a low resistance and it is necessary to reduce the number of contact holes connecting with the wiring layer 36.
Conventionally, in order to lower the resistance of a bit line 30a for the purpose of miniaturizing the memory cells, it is preferable to increase the energy and increase the dosage of the ion implantation that forms the bit line 30a. Furthermore, it is preferable to shorten the distance between the bit lines 30a. However, because the bit line 30a serves as the source region and the drain region, the source region and the drain region are formed with a high energy and high dosage. Therefore, in writing data and the like, if a high voltage is applied between the source region and the drain region (namely, between the bit lines 30a), junction current flows between the source region and the drain region reducing the source-drain breakdown voltage. In addition, reading characteristics for reading data may also be degraded. These issues interfere with the miniaturization of the memory cells.
SUMMARY OF THE INVENTIONThe present invention intends to suppress the reduction of the breakdown voltage between the source and drain and allow the formation of low-resistance bit 20 lines. Thus, an object of the present invention is to provide a semiconductor device that enables miniaturization of memory cells and a manufacturing method therefor.
According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate, a high concentration diffusion region that is formed in the semiconductor substrate, a first low concentration diffusion region that is formed under the high concentration diffusion region and has a lower concentration of impurities than the high concentration diffusion region, and a bit line that includes the high concentration diffusion region and the first low concentration diffusion region and serves as a source region and a drain region. In accordance with the present invention, the junction profile of a bottom portion of the high concentration diffusion region can be reduced, thereby reducing the electric field of the bottom portion even when high voltage is applied between the bit lines. Thus, the junction current between the bottom portions can be suppressed and the source-drain breakdown voltage can be improved. In addition, the high concentration diffusion region can be formed by high energy, high dosage ion implantation and the formation of a low-resistance bit line is possible. Furthermore, the distance between the bit lines can be shortened, thereby providing a semiconductor with miniaturized memory cells.
The semiconductor device may include pocket implantation regions that are formed on both sides of the high concentration diffusion region and are included in the bit line. When the pocket implantation regions are provided and writing characteristics are improved, the junction current increases. However, through the provision of the first low concentration diffusion region, the junction current can be suppressed even when there are pocket implantation regions, thereby improving the source-drain breakdown voltage. Thus, a semiconductor device that enables the miniaturization of memory cells can be provided.
The semiconductor device may be configured so that the width of the first low concentration diffusion region is narrower than that of the high concentration diffusion region. With this structure, improved writing characteristics due to the pocket implantation can be maintained while suppressing the junction current from the bottom portion of the high concentration diffusion region.
The semiconductor device may alternatively be configured so that the width of the first low concentration diffusion region is approximately equal to that of the high concentration diffusion region. With this structure, the first low concentration diffusion region can be formed over the entire bottom surface of the high concentration diffusion region, thereby more effectively suppressing the flow of the junction current.
In addition, the semiconductor device may include second low concentration diffusion regions that are formed on both sides of the high concentration diffusion region and included in the bit line, the second concentration diffusion regions having a lower concentration of impurities than the high concentration diffusion region. With this structure, the junction profile of the side sections of the high concentration diffusion region can be reduced, thereby reducing the electric field of the side sections even when high voltage is applied between the bit lines. Thus, through the provision of the first low concentration diffusion region and the second low concentration diffusion regions, the junction current in the side sections, in addition to the junction current in the bottom portion of the high concentration diffusion region, can be suppressed, and the source-drain breakdown voltage can be further improved.
The semiconductor device may also include an film that is provided on the semiconductor substrate and a word line that is provided on the film and serves as a gate electrode. In addition, the present invention can be a semiconductor device in which the film has multiple charge storage regions under the gate electrode and between the bit lines.
According to another aspect of the present invention, there is provided a manufacturing method for a semiconductor device including the step of forming a high concentration diffusion region that is included in a bit line and serves as a source region and a drain region in a semiconductor substrate and the step of forming a first low concentration diffusion region under the high concentration diffusion region, the first low concentration diffusion region that is included in the bit line and has a lower concentration of impurities than the high concentration diffusion region. In accordance with the present invention, the junction profile of the bottom portion of the high concentration diffusion region can be reduced. Therefore, the electric field of this bottom portion is reduced even when high voltage is applied between the bit lines, thereby suppressing the junction current between the bottom portions and improving the source-drain breakdown voltage. As a result, the high concentration diffusion region can be formed by high energy, high dosage ion implantation, formation of low-resistance bit line is possible, and the distance between the bit lines can be shortened. From the foregoing, a semiconductor that enables miniaturization of memory cells can be provided.
The manufacturing method may include the step of forming a mask layer on the semiconductor substrate, during which the step of forming the high concentration diffusion region and the step of forming the first low concentration diffusion region respectively include the step of performing ion implantation on the semiconductor substrate with the mask layer as a mask.
The manufacturing method may also be configured so that an opening in the mask layer may be expanded by ion implantation, and the step of forming the high concentration diffusion region is performed after the step of forming the first low concentration diffusion region. In addition, the manufacturing method may be configured so that the mask layer is a photoresist layer. Thus, the first low concentration diffusion region can be formed with few manufacturing steps.
The manufacturing method may further be configured so that the mask layer includes a metal or insulating film. With this structure, the width of the high concentration diffusion region and the width of the first concentration diffusion region can be formed approximately equal. Thus, the flow of the junction current can be more effectively suppressed.
Also, the manufacturing method may include the step of forming side walls on the side sections of the mask layer and the step of forming the high concentration diffusion region is a step of performing ion implantation with the mask layer as a mask and the step of forming the first low concentration diffusion region is a step of performing ion implantation with the mask layer and the side walls as the mask. In accordance therewith, the widths of the high concentration diffusion region and the first low. concentration diffusion region can be accurately formed, thereby suppressing fluctuations in transistor characteristics. In addition, through the arbitrary design of the width of the side walls, shift amount of the high concentration diffusion region and the first low concentration diffusion region can be designed arbitrarily. Thus, the desired transistor design becomes possible.
The manufacturing method may also include the step of performing ion implantation with the mask layer as a mask and forming pocket implantation regions included in the bit lines on both sides of the high concentration diffusion region. When the pocket implantation regions are provided and writing characteristics are improved, the junction current increases. However, through the provision of the first low concentration diffusion region, the junction current can be suppressed even when there are pocket implantation regions and, consequently, the source-drain breakdown voltage can be improved. Thus, a manufacturing method of a semiconductor device that enables the miniaturization of the memory cells can be provided.
The manufacturing method may additionally include the of forming second low concentration diffusion regions on both sides of the high concentration diffusion region, the second low concentration diffusion regions having a lower concentration of impurities than the high concentration diffusion region and included in the bit line. Thus, the junction profile of the side sections of the high concentration diffusion region can be reduced, and the electric field of the side sections can be reduced even when high voltage is applied between the bit lines. Therefore, by providing the first low concentration diffusion region, the junction current between the side sections as well as the junction current between the bottom portion of the high concentration region can be suppressed and the source-drain breakdown voltage can further be improved.
The manufacturing method may also include the step of forming an 30 film on the semiconductor substrate and the step of forming a word line serving as a gate electrode on the film.
As described above, in accordance with the present invention, the source-drain breakdown voltage of the transistor can be suppressed and a low resistance bit line can be formed, thereby providing a semiconductor device that enables the miniaturization of the memory cells and a manufacturing method therefor.
A description will now be given, with reference to
In particular, when ion implantation is performed, a depletion layer between the bit lines 30a become closer because a P-type region that has a higher concentration than the semiconductor substrate 10 is formed between the bit lines 30a within the semiconductor substrate 10. Furthermore, because impurities reach deep within the semiconductor substrate 10 by ion implantation, the depletion layer between the bit lines 30a is even closer near the bottom portion, thereby further facilitating the flow of junction current near the bottom portion.
Thus, a first low concentration diffusion region that has a lower impurity concentration than the high concentration diffusion region 22 is formed under the high concentration diffusion region 22. A cross-sectional diagram in accordance with the present embodiment is shown in
In this manner, the junction profile of the bottom portion of the high concentration diffusion region 22 is reduced. Therefore, when high voltage is applied between the bit lines 30b, the electric field of the bottom portion 60 of the high concentration diffusion region 22 is reduced. As a result, the flow of the junction current becomes poorer, and the source-drain breakdown voltage improves. Thus, when the high concentration diffusion region 22 is formed by high energy and high dosage ion implantation, a low-resistance bit line 30b can be formed. In addition, the distance between the bit lines 30b can be shortened. Consequently, the memory cells can be miniaturized. Hereinafter, the embodiments of the present invention are explained.
First EmbodimentA first embodiment of the present invention is an example in which ion implantation is performed with a photoresist and a mask layer.
Next, in
The photoresist 40 is removed and a top oxide film 16 (silicon oxide film) is formed using, for example, the CVD method. In this way, the ONO film 18 composed of the tunnel oxide film 12, the trap film 14, and the top oxide film 16 is formed on the semiconductor substrate 10. A polycrystalline silicon film is then formed and a predetermined area is removed using ordinary exposure and etching methods. In this way, a word line 32 that serves as a gate electrode is formed on the ONO film 18. Subsequently, the flash memory in
In this flash memory, the ONO film 18 is provided on the semiconductor substrate 10 and the word line 32 serving as the gate electrode is provided on the ONO film 18. The semiconductor substrate 10 between the bit lines 30b functions as a channel and the ONO film 18 between the channel and the word line 32 stores electric charge and functions as a non-volatile memory. The charge storing region can be formed in two locations between the bit lines 30b under the word line 32 by switching the source region and the drain region. In other words, two charge storage regions are provided in the ONO film 18 between the bit lines 30b under the word line 32.
A semiconductor in accordance with the first embodiment includes the high concentration diffusion region 22 formed within the semiconductor substrate 10 and a first low concentration diffusion region 24 that has a lower impurity concentration than the high concentration diffusion region 22 and is provided under the high concentration diffusion region 22. Furthermore, the bit line 30b that serves as the source region and the drain region includes the high concentration diffusion region 22 and the first low concentration diffusion region 24. In this manner, by the implementation of the vertical LDD structure and the provision of the first low concentration diffusion region 24 under the high concentration diffusion region 22, the junction profile of the bottom portion 60 of the high concentration diffusion region 22 can be reduced. In addition, the electric field of the bottom portion 60 does not become high, even when high voltage is applied between the bit lines thereby suppressing the junction current between the bottom portions 60 and improving the source-drain breakdown voltage. From the foregoing, it can be seen that the high concentration diffusion region 22 can be formed by high energy, high dosage ion implantation. In addition, the distance between the bit lines 30b can be shortened, thereby miniaturizing the memory cells.
In addition, the pocket implantation regions 28 (to which pocket implantation has been performed) are provided on both sides of the high concentration diffusion region 22, the bit line 30b including the pocket implantation regions 28. When there are pocket implantation regions 28, writing characteristics are improved and the junction current becomes prominent, as explained previously. However, by the provision of the first low concentration diffusion region 24, the junction current can be suppressed and the source-drain breakdown voltage can be improved even when there 35 are the pocket implantation regions 28, enabling miniaturization of the memory cells.
Also, the width of the first low concentration diffusion region 24 is narrower than the high concentration diffusion region 22. Therefore, the improvement in the writing characteristics due to the pocket implantation can be maintained while suppressing the junction current from the bottom portion of the high concentration diffusion region 22.
As in
At the same time, the ion implantation for forming the low concentration diffusion region 24 is, for example, about 1×1013 cm−3 and the photoresist 40 is barely removed, while the opening is barely expanded. Therefore, first, the ion implantation for forming the first low concentration diffusion region 24 is performed and, subsequently, the ion implantation for forming the high concentration diffusion region 22 is performed. In this manner, the width of the high concentration diffusion region can be wider than the width of the first low concentration diffusion region 24.
Furthermore, in addition to the dosage of the pocket implantation being about 3×1013 cm−3, the boron that is the implanted ion has a smaller ion radius than arsenic and, therefore, little of the photoresist 40 is removed, even when the dosage is large. Thus, the pocket implantation is preferably performed after the formation of the high concentration diffusion region 22 because, if the pocket implantation is performed first, arsenic is implanted, even into the pocket implantation region, during the formation of the high concentration diffusion region 22.
Accordingly, the first low concentration diffusion region 24, the high concentration diffusion region 22, and the pocket implantation region 28 can be formed using the same photoresist 40. Advantageously, the first low concentration diffusion region 24 can be formed merely by the addition to the conventional manufacturing method of the step of ion implantation to form the first low concentration diffusion region 24.
Second EmbodimentA semiconductor device in accordance with a second embodiment of the present invention is an example of a semiconductor device wherein the ion implantation is performed using an insulating film as the mask layer.
In
Next, in
In
In accordance with the second embodiment, the vertical direction LDD structure is implemented and the first low concentration diffusion region 24 is provided under the high concentration diffusion region 22. Therefore, the junction current between the bottom portions can be suppressed and the source-drain breakdown voltage can be improved. Thus, miniaturization of the memory cells becomes possible. Furthermore, even with the pocket implantation regions 28, the junction current between the bottom portions can be controlled and the source-drain breakdown voltage can be improved.
Although the silicon oxide film is used as the mask layer 42, any material in which the opening of the mask layer 42 does not expand due to ion implantation can be used. The mask layer 42 is preferably a material that can acquire selectivity with the trap layer 14. For example, through the use of the silicon oxide film, such as in accordance with the second embodiment, selectivity with the silicon nitride film that is the trap layer 14 can be acquired.
In accordance with the second embodiment, the width of the high concentration diffusion region 22 and the width of the first low concentration diffusion region 24 can be made approximately equal by the use of the mask layer 42 of insulating film. In this manner, the concentration diffusion region 24 can be formed over the entire bottom surface of the high concentration diffusion region 22. Thus, the flow of the junction current can be suppressed more effectively.
When improvement in the writing characteristics is prioritized by making the width of the low concentration diffusion region 24 narrower than that of the high concentration diffusion region 22, as in accordance with the first embodiment, the effect of the pocket implantation is further maintained and the writing characteristics can be improved. At the same time, when the suppression of the junction current is prioritized by making the width of the low concentration diffusion region 24 and the high concentration diffusion region 22 approximately equal as in accordance with the second embodiment, the junction current can be further suppressed.
Third EmbodimentA third embodiment is an example of a semiconductor device in which side walls are formed and ion implantation is performed using the insulating film as the mask layer.
In
In
Next, in
In
In accordance with the third embodiment, the vertical direction LDD structure is implemented and the first low concentration diffusion region 24 is provided under the high concentration diffusion region 22, as in accordance with the first embodiment. As a result of this vertical LDD structure, the junction current between the bottom portions can be suppressed and the source-drain breakdown voltage can be improved. Thus, miniaturization of memory cells becomes possible. Furthermore, even when there are pocket implantation regions 28, the junction currents between the bottom portions can be suppressed and the source-drain breakdown voltage can be improved.
In addition, through the use of the silicon oxide film as the mask layer 42, the side walls 46 can be formed on both sides of the mask layer 42, through the high temperature side wall formation step. Aside from silicon oxide film, the mask layer 42 can be any material that can withstand the heat treatment during the formation of the side walls 46. For example, insulation film and metal can be used. In addition, when removing, the mask layer 42 and the side walls 46 are preferably materials that can acquire selectivity with the trap layer 14. For example, through the use of the silicon oxide film as in accordance with the third embodiment, selectivity with the silicon nitride film that is the trap layer 14 can be acquired.
In accordance with the third embodiment, the high concentration diffusion region 22 is formed by ion implantation with the mask layer 42 as the mask, the side walls 46 are formed on the side-sections of the mask layer 42, and the first low concentration diffusion region 24 is formed by ion implantation with the mask layer 42 and the side wall 46 as the mask. In this manner, the width of the first low concentration region 24 can be made narrower than that of the high concentration diffusion region in accordance with the first embodiment. Thus, the effect of the pocket implantation can be maintained, while suppressing the junction current 10 from the bottom portion of the high concentration diffusion region 22.
In accordance with the first embodiment, the width of the opening of the photoresist 40 that is the mask layer is expanded by the ion implantation step for forming the high concentration diffusion region 22, and the width of the high concentration diffusion region 22 is determined by this width. In this case, there is fluctuation in the expansion of the photoresist 40, and the width of the high concentration diffusion region 22 fluctuates. In addition, the amount of expansion of the photoresist 40 varies with the implantation condition and, therefore, it is difficult to arbitrarily decide the shift amount of the high concentration diffusion region 22 and the first low concentration diffusion region 24.
At the same time, in accordance with the third embodiment, the high concentration diffusion region 22 can be formed by ion implantation with the mask layer 42 as the mask, such that the width thereof is formed with favorable controllability. In addition, through the use of the side walls 46, the width of the first low concentration diffusion region 24 can be formed accurately. Therefore, the widths of both the high concentration diffusion region 22 and the first low concentration diffusion region can be accurately formed, thereby suppressing the fluctuation of the transistor characteristics. In addition, through arbitrary decision of the width of the side walls 46, the shift amounts of the high concentration diffusion regions 22 and the first low concentration diffusion regions 24 can be decided arbitrarily. Thus, design in accordance with desired transistors is possible.
As explained previously, when the reduction of manufacturing steps is prioritized, manufacturing in accordance with the first embodiment is preferable. On the other hand, if the suppression of the fluctuation in the transistor characteristics and design enhancement are prioritized, manufacturing in accordance with the third embodiment is preferable.
Fourth EmbodimentA fourth embodiment is an example of a semiconductor device in which second low concentration diffusion regions are formed on both sides of the high concentration diffusion region.
Referring to
In accordance with the fourth embodiment, in addition to the vertical direction LDD structure that is the same as that in accordance with the first embodiment, a horizontal direction LDD structure is implemented and the second low concentration diffusion regions 26 are provided on both sides of the high concentration diffusion region 22. In this manner, the junction profile of the side sections of the high concentration diffusion region 22 can be reduced. Therefore, even when high voltage is applied between the bit lines 30c, the electric field of the side sections does not become high. Thus, the junction current between the bottom portions of the high concentration diffusion region 22 can be suppressed in addition to suppressing the junction current between the side sections, thereby further improving the source-drain breakdown voltage.
Furthermore, the width of the first low concentration diffusion region 24 can be made narrower than that of the high concentration diffusion region 22. Thus, the effect of the pocket implantation can be maintained while suppressing the junction current from the bottom part of the high concentration diffusion region 22.
Furthermore, the first low concentration diffusion region 24, the high concentration diffusion region 22, the pocket implantation regions 28, and the second concentration diffusion regions 26 can be formed using the same photoresist 40. Therefore, the second low concentration diffusion regions 24 can be formed merely by the addition of the step of expanding the opening of the photoresist 40 and the ion implantation step of forming the second low concentration diffusion regions 24 in accordance with the first embodiment. Thus, an increase in manufacturing steps can be reduced.
Fifth EmbodimentA fifth embodiment is an example of a semiconductor device in which the second low concentration diffusion regions are formed on both sides of the high concentration diffusion region using an insulating film mask.
Referring to
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In
In
In accordance with the fifth embodiment, the second concentration diffusion regions 26 are provided on both sides of the high concentration diffusion region 22 as the horizontal direction LDD structure in addition to the vertical direction LDD structure, as in accordance with the fourth embodiment. Thus, the junction current between the side sections, in addition to a junction leak current between the bottom portions of the high concentration diffusion region 22, can be suppressed and the source-drain breakdown voltage can be improved.
Furthermore, through the step of ion implantation using an insulating film or metal mask layer 50 and side walls 52, the width of the high concentration diffusion region 22 can be made approximately equal to the width of the first low concentration diffusion region 24. In this manner, the first low concentration diffusion region 24 can be formed over the bottom portion of the high concentration diffusion region 22. Thus, the flow of the junction current can be more effectively suppressed.
Furthermore, through the formation of the second low concentration diffusion regions 26 with the insulating film or metal mask layer 50 as the mask, the width of the second low concentration diffusion regions 26 can be formed accurately. Furthermore, the side walls 52 are provided on both sides of the mask layer 50 and the high concentration diffusion region 22 and the first low concentration diffusion region 24 are formed. Therefore, the widths of the high concentration diffusion region 22 and the first low concentration diffusion region 24 can be accurately formed. Thus, the fluctuation in the transistor characteristics can be suppressed enabling desired transistor designs.
Sixth EmbodimentA sixth embodiment is an example of a semiconductor device in which the second low concentration diffusion regions are formed on both sides of the high concentration diffusion region using an insulating film mask.
In
In accordance with the sixth embodiment, the second concentration diffusion regions 26 are provided on both sides of the high concentration diffusion region 22 as the horizontal direction LDD structure, in addition to the vertical direction LDD structure, as in accordance with the fourth embodiment and the fifth embodiment. Thus, the junction current between the side sections, in addition to a junction leak current between the bottom portions of the high concentration diffusion region 22, can be suppressed, and the source-drain breakdown voltage can be improved.
The high concentration diffusion region 20 is formed by the ion implantation with the mask layer 50 and the side walls 52 as the mask; in addition, the side walls 54 are provided on both sides of the side walls 52, and the first low concentration diffusion region 24 is formed by ion implantation with the side walls 54 as the mask. Through this, the width of the first low concentration diffusion region 24 can be made narrower than that of the high concentration diffusion region 22, as in accordance with the first embodiment. Thus, the effect of the pocket implantation can be maintained, while suppressing the junction leak current from the bottom portion of the high concentration diffusion region 22.
Furthermore, through the formation of the second low concentration diffusion regions 26 with the insulating film or metal mask layer 50 as the mask, the width of the second low concentration diffusion regions 26 can be formed accurately. Furthermore, the side walls 52 are provided on both sides of the mask layer 50, the high concentration diffusion region 52 is formed, thereby permitting accurate formation of the width of the high concentration diffusion region 22. Furthermore, the side walls 54 are provided on both sides of the side walls 52, the first low concentration diffusion region 24 is formed, thereby permitting accurate formation of the first low concentration diffusion region 24. Thus, the fluctuation in the transistor characteristics can be suppressed and desired transistor designs become possible.
In accordance with the fourth to sixth embodiments, the junction current can be suppressed and the source-drain breakdown voltage can be improved by the second low concentration diffusion regions 26. However, the impurity concentration profile of the side sections of the high concentration diffusion region 22 is reduced and the electric field occurring when voltage is applied between the source region and the drain region is also reduced. Thus, this is disadvantageous to a writing operation in which electrons that have become high energy are implanted in the trap layer 14 within the ONO film 18. At the same time, in accordance with the first to third embodiment, the impurity concentration profile of the side sections of the high concentration diffusion region 22 is steep, and favorable writing characteristics can be obtained.
Therefore, when the improvement of the source-drain breakdown voltage is prioritized, the use of the first to third embodiments is preferable. On the other when the improvement of the writing characteristics is prioritized, the use of the fourth to sixth embodiments is preferable.
Although embodiments of the present invention have been explained above, the present invention is not limited to the specific embodiments described, and various changes and modifications can be made without departing from the principles and spirit of the invention, the scope of which is defined in the claims hereinbelow. For example, in a flash memory in accordance with the first to sixth embodiments, the ONO film 18 is provided on the semiconductor substrate 10, the word line 32 including a gate electrode is provided on the ONO film 18, and the charge storage regions are present in two locations within the ONO film 18, between the bit lines 30b and 30c, under the word line 32. Even if the configuration is not as such, if a semiconductor device has a bit line with the bit line structure of the present invention, serving as the source region and the drain region, and is formed within the semiconductor substrate, the effects of the present invention can be achieved.
Claims
1. A computer readable media comprising computer-executable instructions stored therein for fabricating a semiconductor device, the computer-executable instructions comprising:
- instructions to form a high concentration diffusion region in a semiconductor substrate, the high concentration diffusion region being included in a source region and a drain region; and
- instructions to form a first low concentration diffusion region under the high concentration diffusion region, the first low concentration diffusion region having a lower concentration than the high concentration region and included in the bit line.
2. The computer readable media of claim 1, further comprising instructions to form a mask layer over the semiconductor substrate, wherein each of the forming of the high concentration diffusion region and the forming of the first low concentration diffusion region includes instructions to implant ions in the semiconductor substrate by using the mask layer.
3. The computer readable media of claim 2, wherein an opening in the mask layer is expanded by ion implantation, and wherein the formation of the high concentration diffusion region is performed after the formation of the first low concentration diffusion region.
4. The computer readable media of claim 3, wherein the mask layer includes a photo resist layer.
5. The computer readable media of claim 2, wherein the mask layer includes a metal or insulator.
6. The computer readable media of claim 1 further comprising instructions to form sidewalls at both sides of the mask layer, wherein:
- the formation of the high concentration diffusion region implants ions in the semiconductor substrate by using the mask layer as a mask for ion implantation; and
- the formation of the first low concentration diffusion region implants ions in the substrate by using the mask layer and the sidewalls as a mask for ion implantation.
7. The computer readable media of claim 2, further comprising instructions to form pocket ion implantation regions, at both sides of the high concentration diffusion region, by using the mask layer as a mask for pocket ion implantation, the pocket ion implantation regions included in the bit line.
8. The computer readable media of claim 2, further comprising instructions to form second low concentration diffusion regions at both sides of the high concentration diffusion region, the second low concentration diffusion regions having a lower concentration than the high concentration diffusion region and included in the bit line.
9. The computer readable media of claim 1 further comprising:
- instructions to form an ONO film on the semiconductor substrate; and
- instructions to form a wide line on the ONO film, the wide line including a gate electrode.
10. The computer readable media of claim 1, wherein a width of the first low concentration region is less than a width of the high concentration diffusion region.
11. The computer readable media of claim 1, wherein a width of the first low concentration region is equal to a width of the high concentration diffusion region.
Type: Application
Filed: Dec 12, 2011
Publication Date: Apr 5, 2012
Inventor: Masatomi OKANISHI (Aizuwakamatsu-shi)
Application Number: 13/323,579
International Classification: H01L 21/336 (20060101);