Abstract: A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.

Abstract: A semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption in a simple configuration is provided. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.

Abstract: Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.

Abstract: A Y selection line for write for controlling operations of a column selection switch within a write amplifier and a Y selection line for read for controlling operations of a column selection switch within a read amplifier are provided individually and the column selection switch within the read amplifier is set to the non-operating condition during the write operation. Accordingly, a through-current during the write operation may be reduced. In this case, the write IO line and read IO line are allocated crossing sense amplifier columns, while the column selection line for write and column selection line for read are allocated in parallel to the sense amplifier columns.

Abstract: Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.

Abstract: The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout.

Abstract: Provided are an ester group-containing poly(imide-azomethine)copolymer having low linear thermal expansion coefficient; a production method thereof; an ester group-containing poly(amide acid-azomethine)copolymer to serve as the precursor of the poly(imide-azomethine)copolymer; a positive photosensitive composition including the poly(amide acid-azomethine)copolymer and a photosensitizer; a method for forming a fine pattern of an ester group-containing poly(imide-azomethine)copolymer from the composition; and a method for forming a fine pattern of an ester group-containing poly(imide-azomethine)copolymer by etching a photosensitizer-free, ester group-containing poly(imide-azomethine)copolymer in an alkaline solution.

Abstract: A semiconductor integrated circuit device realizing high integration and a simplified manufacturing process. The circuit includes a gate insulator with a first film thickness, a first N-channel MOSFET and a first P-channel MOSFET, in which a polysilicon layer consists of a gate electrode including an N-type impurity dose, and a gate insulator with a second film thickness thinner than the first film thickness. The circuit also includes a second N-channel MOSFET and a second P-channel MOSFET in which the polysilicon layers are doped with N-type impurity and P-type impurity, respectively. Gate electrodes of said first N-channel MOSFET and first P-channel MOSFET are formed as one body and connected to each other.

Abstract: The first film of the present invention is a film produced by solidifying a polybenzazole precursor that has been oriented in a given direction by the application of a magnetic or electric field. The second film of the present invention is a film produced by solidifying a polybenzazole that has been oriented in a given direction by the application of a magnetic or electric field. The first and second films have a strong anisotropy.

Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

Abstract: Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.

Abstract: A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.

Abstract: Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.

Abstract: The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout.

Abstract: Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.

Abstract: A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: A semiconductor memory device that satisfies needs of both a large number of memory banks and a higher operation speed is provided. A semiconductor memory device includes a plurality of data terminal pads, and a plurality of memory banks independently subject to memory access. Each of the memory banks is divided into a plurality of submemory banks. The data terminal pads are also divided into a plurality of groups so as to be associated with submemory banks obtained by the division. Blocks each including submemory banks obtained by the division and data terminal pads associated with the submemory banks are arranged so as not to overlap each other on a semiconductor chip.

Abstract: The first film of the present invention is a film produced by solidifying a polybenzazole precursor that has been oriented in a given direction by the application of a magnetic or electric field. The second film of the present invention is a film produced by solidifying a polybenzazole that has been oriented in a given direction by the application of a magnetic or electric field. The first and second films have a strong anisotropy.