Patents by Inventor Masatoshi Morikawa
Masatoshi Morikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240026641Abstract: An upper revolving structure 3 of a hydraulic excavator 1 includes a heat exchanger room 12 and a pump room 13 that respectively accommodate first and second antenna devices 24, 27 removed from first and second antenna attaching tools 25, 28 in a state where antenna-side cables 26A, 29A are connected to the first and second antenna devices 24, 27, and first and second antenna retaining tools 30, 33 that are arranged inside the heat exchanger room 12 and the pump room 13 to retain the first and second antenna devices 24, 27 removed from the first and second antenna attaching tools 25, 28. A housing cover 11 is configured to cover the heat exchanger room 12 and the pump room 13 in an openable or closable manner and include a left rear side door 16 and a right side door 19 that can be locked in a state where the heat exchanger room 12 and the pump room 13 are closed.Type: ApplicationFiled: November 10, 2021Publication date: January 25, 2024Inventors: Masatoshi MORIKAWA, Shigeru HIRASAWA
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Publication number: 20230366174Abstract: A work machine includes a work implement provided to a machine body, a posture sensor that senses posture information regarding the work implement, a controller configured to compute a specific position of the work implement on the basis of the posture information, set a limited area that the work implement is prohibited from entering, compute a movable distance as a distance between the limited area and the specific position of the work implement, and limit operation of the work implement according to the movable distance to prevent the work implement from entering the limited area, and an input device for inputting to the controller input information input by an operation of an operator.Type: ApplicationFiled: January 6, 2022Publication date: November 16, 2023Inventors: Shinji NISHIKAWA, Hiroaki TANAKA, Masatoshi MORIKAWA, Akihiro NARAZAKI
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Publication number: 20230366171Abstract: An object of the present invention is to provide a work machine that is capable of flexibly setting an entry-prohibited area for a work device according to an operator's intention. To achieve this, a controller 40 sets, as a first position, the position of a work tool 8 that is located when a setting switch 33 is operated, and sets, as a second position, the position of the work tool 8 that is located when the setting switch 33 is operated after the setting of the first position. Further, the controller 40 sets, as a boundary surface of an entry-prohibited area, a plane 70 that passes through a first reference point A and a second reference point B and that is perpendicular to a ground contact surface of a lower track structure 1. The first reference point A is one of a plurality of reference points 8L and 8R on the work tool 8 located at the first position, the plurality of reference points 8L and 8R being preset on the work tool 8.Type: ApplicationFiled: November 11, 2021Publication date: November 16, 2023Inventors: Masatoshi MORIKAWA, Shinji NISHIKAWA, Hiroaki TANAKA
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Publication number: 20230349129Abstract: A main controller of a work machine computes target position information of an entry-prohibited area plane on the basis of operation information of a console switch 11 or a monitor operation device, decides, on the basis of the target position information of the entry-prohibited area plane, whether or not a distance r1 between a target position M of the entry-prohibited area plane and the center O of swing action of an upper swing structure is greater than a threshold value set based on a distance r2 from the center O of swing action of the upper swing structure to a rear end of the upper swing structure, validates the target position information of the entry-prohibited area plane when the distance r1 is greater than the threshold value, and sets the entry-prohibited area plane at the target position M.Type: ApplicationFiled: November 10, 2021Publication date: November 2, 2023Inventors: Masatoshi MORIKAWA, Shinji NISHIKAWA, Hiroaki TANAKA
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Patent number: 11248364Abstract: To control a rate of increase of a delivery flow rate of a pump for a swing operation in response to a moment of inertia and an operation amount and to achieve both energy efficiency and operability with respect to the swing operation, a work machine including a swing structure 2 disposed on an upper portion of a track structure 1, a work implement 3 disposed in the swing structure 2, a swing motor 16, a hydraulic pump 22, a regulator 24, a directional control valve 31, and an operation device 34 further includes: a target maximum flow rate calculation section 53 configured to calculate a target maximum flow rate Qmax of the pump to correspond to a swing operation amount Ps; a flow rate rate-of-increase calculation section 55 configured to calculate a rate of increase dQ of a command flow rate of the hydraulic pump 22 on a basis of the moments of inertia of the swing structure 2 and the work implement 3 and the swing operation amount Ps; a command flow rate calculation section 56 configured to calculate a comType: GrantFiled: February 24, 2017Date of Patent: February 15, 2022Assignee: Hitachi Construction Machinery Co., Ltd.Inventors: Masatoshi Morikawa, Shinya Imura, Shinji Nishikawa
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Publication number: 20210207342Abstract: To control a rate of increase of a delivery flow rate of a pump for a swing operation in response to a moment of inertia and an operation amount and to achieve both energy efficiency and operability with respect to the swing operation, a work machine including a swing structure 2 disposed on an upper portion of a track structure 1, a work implement 3 disposed in the swing structure 2, a swing motor 16, a hydraulic pump 22, a regulator 24, a directional control valve 31, and an operation device 34 further includes: a target maximum flow rate calculation section 53 configured to calculate a target maximum flow rate Qmax of the pump to correspond to a swing operation amount Ps; a flow rate rate-of-increase calculation section 55 configured to calculate a rate of increase dQ of a command flow rate of the hydraulic pump 22 on a basis of the moments of inertia of the swing structure 2 and the work implement 3 and the swing operation amount Ps; a command flow rate calculation section 56 configured to calculate a comType: ApplicationFiled: February 24, 2017Publication date: July 8, 2021Inventors: Masatoshi MORIKAWA, Shinya IMURA, Shinji NISHIKAWA
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Patent number: 8786002Abstract: In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.Type: GrantFiled: June 2, 2011Date of Patent: July 22, 2014Assignee: Renesas Electronics CorporationInventors: Masao Kondo, Masatoshi Morikawa, Satoshi Goto
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Patent number: 8482058Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).Type: GrantFiled: June 1, 2012Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
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Publication number: 20130002338Abstract: SOI MOSFETs are used for the transistors for switching of an antenna switch and yet harmonic distortion is significantly reduced. Capacitance elements are respectively added to either the respective drains or gates of the transistors comprising the through MOSFET group of reception branch of the antenna switch. This makes the voltage amplitude between source and gate and that between drain and gate different from each other. As a result, the voltage dependence of source-drain parasitic capacitance becomes asymmetric with respect to the polarity of voltage. This asymmetry property produces signal distortion having similar asymmetry property. Therefore, the following can be implemented by setting it so that it has the same amplitude as that of second-harmonic waves arising from the voltage dependence of substrate capacitance and a phase opposite to that of the same: second-order harmonic distortion can be canceled out and thus second-order harmonic distortion can be reduced.Type: ApplicationFiled: September 7, 2012Publication date: January 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masao KONDO, Satoshi GOTO, Masatoshi MORIKAWA
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Publication number: 20120235250Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).Type: ApplicationFiled: June 1, 2012Publication date: September 20, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
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Patent number: 8232595Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).Type: GrantFiled: May 19, 2011Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
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Publication number: 20110316062Abstract: In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.Type: ApplicationFiled: June 2, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masao KONDO, Masatoshi MORIKAWA, Satoshi GOTO
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Patent number: 8080831Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.Type: GrantFiled: May 21, 2010Date of Patent: December 20, 2011Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
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Publication number: 20110254087Abstract: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n? type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.Type: ApplicationFiled: June 24, 2011Publication date: October 20, 2011Inventors: Tomoyuki MIYAKE, Masatoshi Morikawa, Yutaka Hoshino, Makoto Hatori
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Publication number: 20110220999Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).Type: ApplicationFiled: May 19, 2011Publication date: September 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
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Patent number: 7994567Abstract: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n? type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.Type: GrantFiled: June 25, 2010Date of Patent: August 9, 2011Assignee: Renesas Electronics CorporationInventors: Tomoyuki Miyake, Masatoshi Morikawa, Yutaka Hoshino, Makoto Hatori
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Patent number: 7982263Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).Type: GrantFiled: October 30, 2009Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
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Publication number: 20110127594Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.Type: ApplicationFiled: May 21, 2010Publication date: June 2, 2011Inventors: Fumitaka NAKAYAMA, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
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Publication number: 20110001543Abstract: SOI MOSFETs are used for the transistors for switching of an antenna switch and yet harmonic distortion is significantly reduced. Capacitance elements are respectively added to either the respective drains or gates of the transistors comprising the through MOSFET group of reception branch of the antenna switch. This makes the voltage amplitude between source and gate and that between drain and gate different from each other. As a result, the voltage dependence of source-drain parasitic capacitance becomes asymmetric with respect to the polarity of voltage. This asymmetry property produces signal distortion having similar asymmetry property. Therefore, the following can be implemented by setting it so that it has the same amplitude as that of second-harmonic waves arising from the voltage dependence of substrate capacitance and a phase opposite to that of the same: second-order harmonic distortion can be canceled out and thus second-order harmonic distortion can be reduced.Type: ApplicationFiled: June 11, 2010Publication date: January 6, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masao KONDO, Satoshi GOTO, Masatoshi MORIKAWA
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Publication number: 20100258876Abstract: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n? type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Inventors: Tomoyuki Miyake, Masatoshi Morikawa, Yutaka Hoshino, Makoto Hatori