Patents by Inventor Masatoshi Morikawa

Masatoshi Morikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6897728
    Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: May 24, 2005
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
  • Publication number: 20050098851
    Abstract: Plural elements forming a high frequency device in one chip are provided by forming a resistor element and the lower electrode of a capacitor element from one identical polycrystal silicon film over a substrate; forming the gate electrode of a power MISFET, upper electrode of the capacitor element, gate electrode of an n-channel type MISFET and gate electrode of a p-channel type MISFET from an identical polycrystal silicon film different from the other polycrystal silicon film and above and a WSi film; forming a capacitor element having a wiring formed on a silicon oxide film deposited over the substrate as a lower electrode and a wiring formed on the silicon oxide film as the upper electrode in the region MIN; forming a spiral coil in a region IND using an aluminum alloy film identical with that deposited on a silicon oxide film; and forming a bonding pad in a region PAD.
    Type: Application
    Filed: September 26, 2003
    Publication date: May 12, 2005
    Inventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
  • Publication number: 20050051814
    Abstract: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n? type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.
    Type: Application
    Filed: July 30, 2004
    Publication date: March 10, 2005
    Inventors: Tomoyuki Miyake, Masatoshi Morikawa, Yutaka Hoshino, Makoto Hatori
  • Patent number: 6865399
    Abstract: In a mobile telephone apparatus corresponding to dual-band provided with an RF power module to operate in two kinds of different frequencies, a common harmonics control circuit is provided to the output circuit of such RF power module to realize higher efficiency in view of controlling respective harmonics power for both band frequencies. Moreover, a means for selectively setting the bias is also provided so that the maximum efficiency can be attained depending on the output power required with respective communication systems with the bias control signal output from the CPU of the control unit interlocking with selection of frequency of the mobile telephone apparatus body.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toru Fujioka, Isao Yoshida, Mineo Katsueda, Masatoshi Morikawa, Yoshikuni Matsunaga, Kenji Sekine, Osamu Kagaya
  • Publication number: 20050017296
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Application
    Filed: August 19, 2004
    Publication date: January 27, 2005
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Publication number: 20050003573
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Application
    Filed: July 26, 2004
    Publication date: January 6, 2005
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Patent number: 6815707
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Patent number: 6797594
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: September 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Patent number: 6707102
    Abstract: A power MOSFET for a high frequency amplification element having good output power characteristics and high frequency characteristics is described. In the power MOSFET, a shield conductive film electrically connected to via an insulating film is arranged over a drain-offset semiconductor region. A wiring for a drain electrode is so arranged as to extent in parallel to the shield conductive film at one end side of the shield conductive film. On the other hand, a wiring for the gate electrode, a wiring for a source electrode and a gate shunt wiring are arranged in this order to extend in parallel to each other at the other end side of the shield conductive film. The shield conductive film is so formed that the thickness thereof is smaller than that of the wiring for the gate electrode. In this way, the input and output capacitances of the MOSFET can be decreased.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: March 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Morikawa, Mio Shindo, Isao Yoshida, Kenichi Nagura
  • Publication number: 20040012445
    Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).
    Type: Application
    Filed: July 8, 2003
    Publication date: January 22, 2004
    Applicants: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
  • Patent number: 6617927
    Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: September 9, 2003
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
  • Patent number: 6605842
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: August 12, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Publication number: 20030062537
    Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 3, 2003
    Inventors: Nobuyuki Sugii, Masatoshi Morikawa, Isao Yoshida, Katsuyoshi Washio
  • Patent number: 6535069
    Abstract: A radio frequency power amplifier module for a dual-band type mobile communication apparatus that can transmit and receive a first frequency f1 and second frequency f2 (f2=2×f1). It includes a drive stage amplifier having the gain peaks at f1 and f2 with a matching circuit and a radio frequency power output circuit including a radio frequency power output transistor. The output circuit has a transmission line connected to the drain end of the output transistor, a parallel resonance circuit connected in series to the transmission line to resonate at harmonics of a frequency twice the frequency f2, a series resonance circuit provided between one end of the resonance circuit and the ground to resonate at harmonics of a frequency twice the frequency f2 and an output matching circuit provided in series to the other end of the parallel resonance circuit for matching with f1 and f2.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 18, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toru Fujioka, Isao Yoshida, Mineo Katsueda, Masatoshi Morikawa, Yoshikuni Matsunaga, Kenji Sekine, Osamu Kagaya
  • Patent number: 6528848
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: March 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Patent number: 6492872
    Abstract: A high frequency power amplifier module is provided for improving output controllability. A wireless communication apparatus incorporates a high frequency power amplifier module in a multi-stage configuration including a plurality of cascaded MOSFETS. The power amplifier module comprises a bias circuit for generating a gate voltage in response to a power control voltage (vapc) generated based on a power control signal of the wireless communication apparatus. The gate voltage has a bias pattern which presents smaller fluctuations in output power in response to a control voltage (Vapc) in a region near a threshold voltage (Vth) of the MOSFETs in respective amplification stages. In this way, the controllability for the output power is improved. More specifically, the power amplifier module has a gate bias circuit for generating the gate voltage (Vg) which follows a gate voltage pattern.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: December 10, 2002
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Toru Fujioka, Yoshikuni Matsunaga, Isao Yoshida, Masatoshi Morikawa, Masao Hotta, Tetsuaki Adachi
  • Publication number: 20020167088
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Application
    Filed: July 2, 2002
    Publication date: November 14, 2002
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Publication number: 20020109549
    Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).
    Type: Application
    Filed: April 16, 2002
    Publication date: August 15, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
  • Patent number: 6433639
    Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the, EDGE (for a linear amplifying action).
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: August 13, 2002
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
  • Publication number: 20020089380
    Abstract: A radio frequency power amplifier module for a dual-band type mobile communication apparatus that can transmit and receive the first frequency f1 and the second frequency f2 (f2=2×f1) is structured as explained below.
    Type: Application
    Filed: February 28, 2002
    Publication date: July 11, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Toru Fujioka, Isao Yoshida, Mineo Katsueda, Masatoshi Morikawa, Yoshikuni Matsunaga, Kenji Sekine, Osamu Kagaya