Patents by Inventor Masatoshi Nishikawa
Masatoshi Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11631691Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.Type: GrantFiled: May 18, 2020Date of Patent: April 18, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Kiyohiko Sakakibara
-
Patent number: 11587943Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures.Type: GrantFiled: September 1, 2020Date of Patent: February 21, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Akio Nishida
-
Patent number: 11487454Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.Type: GrantFiled: December 5, 2019Date of Patent: November 1, 2022Assignee: SanDisk Technologies LLCInventors: Masatoshi Nishikawa, Hardwell Chibvongodze
-
Patent number: 11404122Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.Type: GrantFiled: November 23, 2020Date of Patent: August 2, 2022Assignee: SanDisk Technologies LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
-
Patent number: 11222954Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.Type: GrantFiled: March 24, 2020Date of Patent: January 11, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Hardwell Chibvongodze, Masatoshi Nishikawa
-
Patent number: 11189335Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.Type: GrantFiled: November 13, 2019Date of Patent: November 30, 2021Assignee: SanDisk Technologies LLCInventors: Masatoshi Nishikawa, Hardwell Chibvongodze, Ken Oowada
-
Publication number: 20210305384Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Zhixin CUI, Hardwell CHIBVONGODZE, Masatoshi NISHIKAWA
-
Patent number: 11094715Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.Type: GrantFiled: July 2, 2020Date of Patent: August 17, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Masatoshi Nishikawa, Ken Oowada
-
Patent number: 11081185Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.Type: GrantFiled: June 18, 2019Date of Patent: August 3, 2021Assignee: SanDisk Technologies LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
-
Patent number: 11043537Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. Protruding tip portions are formed on each of the sacrificial material layers around the memory openings. A plurality of insulating spacers is formed within each memory opening between each vertically neighboring pair of tip portions of the sacrificial material layers. A phase change memory material and a vertical bit line are formed within each of the memory openings. The phase change memory material can be formed as a vertical stack of discrete annular phase change memory material portions, or can be formed as a continuous phase change memory material layer. Each of the sacrificial material layer can be replaced by an electrically conductive layer.Type: GrantFiled: June 13, 2019Date of Patent: June 22, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yuji Takahashi, Masatoshi Nishikawa, Wei Kuo Shih
-
Publication number: 20210173559Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.Type: ApplicationFiled: December 5, 2019Publication date: June 10, 2021Applicant: SanDisk Technologies LLCInventors: Masatoshi Nishikawa, Hardwell Chibvongodze
-
Patent number: 11024385Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.Type: GrantFiled: May 17, 2019Date of Patent: June 1, 2021Assignee: SanDisk Technologies LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
-
Patent number: 11024635Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.Type: GrantFiled: May 21, 2020Date of Patent: June 1, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang
-
Publication number: 20210142841Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Applicant: SanDisk Technologies LLCInventors: Masatoshi Nishikawa, Hardwell Chibvongodze, Ken Oowada
-
Patent number: 10991706Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.Type: GrantFiled: August 30, 2019Date of Patent: April 27, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Jayavel Pachamuthu
-
Patent number: 10991705Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.Type: GrantFiled: August 30, 2019Date of Patent: April 27, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Jayavel Pachamuthu
-
Patent number: 10964752Abstract: A vertically alternating sequence of insulating layers and sacrificial material layers is formed over a substrate. Line trenches extending along a first horizontal direction are formed through the vertically alternating sequence. The vertically alternating sequence is divided into vertically alternating stacks of insulating strips and sacrificial material strips. Laterally alternating sequences of memory opening fill structures and dielectric pillar structures are formed within the line trenches. Each of the memory opening fill structures includes a respective vertical bit line and memory material portion located between each laterally neighboring pair of the sacrificial material strip and the vertical bit line.Type: GrantFiled: June 13, 2019Date of Patent: March 30, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yuji Takahashi, Masatoshi Nishikawa, Wei Kuo Shih
-
Publication number: 20210082506Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.Type: ApplicationFiled: November 23, 2020Publication date: March 18, 2021Applicant: SANDISK TECHNOLOGIES LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
-
Patent number: 10930674Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.Type: GrantFiled: May 20, 2020Date of Patent: February 23, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang
-
Publication number: 20210035999Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.Type: ApplicationFiled: August 30, 2019Publication date: February 4, 2021Inventors: Masatoshi NISHIKAWA, Jayavel PACHAMUTHU