Patents by Inventor Masatoshi Nishikawa
Masatoshi Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170148808Abstract: An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an etchant to remove the sacrificial material layers to form lateral recesses and to provide a reactant for depositing electrically conductive layers in the lateral recesses. By distributing the access openings across the entirety of the openings and eliminating the need to employ backside trenches for replacement of the sacrificial material layers, the size and lateral extent of backside trenches can be reduced to a level sufficient to accommodate only backside contact via structures.Type: ApplicationFiled: July 26, 2016Publication date: May 25, 2017Inventors: Masatoshi NISHIKAWA, Masafumi MIYAMOTO, James KAI
-
Publication number: 20170148809Abstract: Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.Type: ApplicationFiled: July 26, 2016Publication date: May 25, 2017Inventors: Masatoshi NISHIKAWA, Masafumi MIYAMOTO, Hiroyuki OGAWA
-
Patent number: 9646981Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.Type: GrantFiled: June 15, 2015Date of Patent: May 9, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Masahide Matsumoto, Yuki Mizutani, Hiroaki Koketsu
-
Publication number: 20170125430Abstract: A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Masatoshi NISHIKAWA, Hiroaki KOKETSU, Fumiaki TOYAMA, Junji OH
-
Patent number: 9620512Abstract: A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.Type: GrantFiled: October 28, 2015Date of Patent: April 11, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Hiroaki Koketsu, Fumiaki Toyama, Junji Oh
-
Patent number: 9616698Abstract: A bookbinding apparatus includes an application roller that applies glue onto a back edge face of a sheet bundle and a bookbinding control unit that positions the application roller onto the back edge face and causes the roller to execute glue application. The bookbinding apparatus applies a required amount of glue determined by a sheet bundle thickness by, after applying side glues to both side surfaces of the sheet bundle, bringing the application roller in contact with a first position within a central region on the back edge face and rotating the roller in a forward direction, bringing the application roller in contact with a second position between the first position and a right side of the sheet bundle, and rotating the roller in the forward direction. The glue is leveled to form a flat layer of adhesive with an adequate thickness.Type: GrantFiled: April 29, 2014Date of Patent: April 11, 2017Assignee: RISO KAGAKU CORPORATIONInventors: Yoshihiro Noguchi, Atsushi Hiroshima, Masatoshi Nishikawa
-
Publication number: 20170092654Abstract: An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the alternating stack. A backside trench is formed and the sacrificial material layers are replaced with electrically conductive layers. After formation of an insulating spacer in the trench, an epitaxial pedestal structure is grown from a semiconductor portion underlying the backside trench. A source region is formed by introducing dopants into the epitaxial pedestal structure and an underlying semiconductor portion during and/or after epitaxial growth. Alternatively, the backside trench can be formed concurrently with formation of memory openings. An epitaxial pedestal structure can be formed concurrently with formation of epitaxial channel portions at the bottom of each memory opening.Type: ApplicationFiled: September 28, 2015Publication date: March 30, 2017Inventors: Masatoshi NISHIKAWA, Kiyohiko SAKAKIBARA, Hiroyuki OGAWA, Shuji MINAGAWA
-
Patent number: 9589981Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.Type: GrantFiled: June 15, 2015Date of Patent: March 7, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Hiroaki Koketsu, Johann Alsmeier
-
Publication number: 20160365351Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.Type: ApplicationFiled: June 15, 2015Publication date: December 15, 2016Inventors: Masatoshi NISHIKAWA, Ryoichi HONMA, Toru MIWA, Masahide MATSUMOTO, Yuki MIZUTANI, Hiroaki KOKETSU
-
Publication number: 20160365352Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.Type: ApplicationFiled: June 15, 2015Publication date: December 15, 2016Inventors: Masatoshi NISHIKAWA, Ryoichi HONMA, Toru MIWA, Hiroaki KOKETSU, Johann ALSMEIER
-
Publication number: 20160351709Abstract: A field effect transistor having a higher breakdown voltage can be provided by forming a contiguous dielectric material layer over gate stacks, forming via cavities laterally spaced from the gate stacks, selectively depositing a single crystalline semiconductor material, and converting upper portions of the deposited single crystalline semiconductor material into elevated source/drain regions. Lower portions of the selectively deposited single crystalline semiconductor material in the via cavities can have a doping of a lesser concentration, thereby effectively increasing the distance between two steep junctions at edges of a source region and a drain region. Optionally, embedded active regions for additional devices can be formed prior to formation of the contiguous dielectric material layer. Raised active regions contacting a top surface of a substrate can be formed simultaneously with formation of the elevated active regions that are vertically spaced from the top surface.Type: ApplicationFiled: May 28, 2015Publication date: December 1, 2016Inventors: Masatoshi NISHIKAWA, Akira INOUE, Fumiaki TOYAMA
-
Publication number: 20140321948Abstract: A bookbinding apparatus includes an application roller that applies glue onto a back edge face of a sheet bundle and a bookbinding control unit that positions the application roller onto the back edge face and causes the roller to execute glue application. The bookbinding apparatus applies a required amount of glue determined by a sheet bundle thickness by, after applying side glues to both side surfaces of the sheet bundle, bringing the application roller in contact with a first position within a central region on the back edge face and rotating the roller in a forward direction, bringing the application roller in contact with a second position between the first position and a right side of the sheet bundle, and rotating the roller in the forward direction. The glue is leveled to form a flat layer of adhesive with an adequate thickness.Type: ApplicationFiled: April 29, 2014Publication date: October 30, 2014Applicant: RISO KAGAKU CORPORATIONInventors: Yoshihiro NOGUCHI, Atsushi HIROSHIMA, Masatoshi NISHIKAWA
-
Patent number: 8563382Abstract: A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration.Type: GrantFiled: March 7, 2012Date of Patent: October 22, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Masatoshi Nishikawa
-
Patent number: 8409958Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.Type: GrantFiled: July 26, 2011Date of Patent: April 2, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Katsuaki Ookoshi, Masatoshi Nishikawa, Yosuke Shimamune
-
Patent number: 8329570Abstract: A method of manufacturing a semiconductor device, comprising, forming a first gate electrode in a first region of a semiconductor substrate and forming a second gate electrode in a second region of the semiconductor substrate, forming a first sidewall along a lateral wall of the first gate electrode and forming a second sidewall along a lateral wall of the second gate electrode, forming an oxide film to cover the semiconductor substrate, the first gate electrode, the second gate electrode, the first sidewall and the second sidewall, forming a resist above the oxide film to cover the first region, removing the oxide film in the second region by etching the oxide film with the resist serving as a mask, removing the resist, and executing a plasma process by using a gas containing chlorine with respect to the semiconductor substrate and the oxide film in the first region.Type: GrantFiled: March 31, 2011Date of Patent: December 11, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Masahiro Fukuda, Ken Sugimoto, Masatoshi Nishikawa
-
Patent number: 8222706Abstract: A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration.Type: GrantFiled: September 9, 2010Date of Patent: July 17, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Masatoshi Nishikawa
-
Publication number: 20120164806Abstract: A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration.Type: ApplicationFiled: March 7, 2012Publication date: June 28, 2012Applicant: FUJISU SEMICONDUCTOR LIMITEDInventor: Masatoshi NISHIKAWA
-
Publication number: 20120058610Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.Type: ApplicationFiled: July 26, 2011Publication date: March 8, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Katsuaki Ookoshi, Masatoshi Nishikawa, Yosuke Shimamune
-
Publication number: 20110250748Abstract: A method of manufacturing a semiconductor device, comprising, forming a first gate electrode in a first region of a semiconductor substrate and forming a second gate electrode in a second region of the semiconductor substrate, forming a first sidewall along a lateral wall of the first gate electrode and forming a second sidewall along a lateral wall of the second gate electrode, forming an oxide film to cover the semiconductor substrate, the first gate electrode, the second gate electrode, the first sidewall and the second sidewall, forming a resist above the oxide film to cover the first region, removing the oxide film in the second region by etching the oxide film with the resist serving as a mask, removing the resist, and executing a plasma process by using a gas containing chlorine with respect to the semiconductor substrate and the oxide film in the first region.Type: ApplicationFiled: March 31, 2011Publication date: October 13, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masahiro Fukuda, Ken Sugimoto, Masatoshi Nishikawa
-
Publication number: 20110057270Abstract: A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration.Type: ApplicationFiled: September 9, 2010Publication date: March 10, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Masatoshi NISHIKAWA