Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

Abstract: A semiconductor structure can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and capacitor pillar structures vertically extending through the first alternating stack. Each of the capacitor pillar structures can include a node dielectric and a semiconductor material portion that is laterally surrounded by the node dielectric. A first electrode layer of a capacitor includes the semiconductor material portions, and a second electrode layer of the capacitor includes the electrically conductive layers. Alternatively or additionally, a first dielectric fill material portion can extend through the alternating stack and can include a plurality of capacitor via cavities. A capacitor can be provided within the plurality of capacitor via cavities.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, and bit lines overlying the memory stack structures. Vertical discharge transistors are provided, each of which includes a respective vertical discharge transistor channel that extends through a second alternating stack of second insulating layers and second electrically conductive layers laterally spaced from the first alternating stack.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, and bit lines overlying the memory stack structures. Vertical discharge transistors are provided, each of which includes a respective vertical discharge transistor channel that extends through a second alternating stack of second insulating layers and second electrically conductive layers laterally spaced from the first alternating stack.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.

Abstract: At least one diode, lower-level metal interconnect structures embedded within lower-level dielectric material layers, and a doped semiconductor material layer are formed over a semiconductor substrate. An electrically conductive path is provided between the at least one diode and the doped semiconductor material layer. An alternating stack of insulating layers and spacer material layers and memory stack structures extending therethrough are formed above the doped semiconductor material layer. A backside trench is formed through the alternating stack. The electrically conductive path is employed during plasma etch processes employed to form the memory stack structures and the backside trench to provide a discharge path for accumulated electrical charges. The electrically conductive path is subsequently disconnected by removing a conductive component underlying the backside trench. The spacer material layers can be replaced with electrically conductive layers employing the backside trench.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a substrate, memory stack structures extending through the alternating stack and containing a respective vertical semiconductor channel and a respective memory film, drain select gate electrodes located over the alternating stack, extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction, and a dielectric cap layer located between adjacent drain select gate electrodes. An air gap is located between adjacent drain select gate electrodes in the dielectric cap layer.

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate, the source-level material layers containing a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the substrate-level material layers, memory stack structures extending through the alternating stack, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel having a bottom surface that contacts a respective horizontal surface of the source contact layer, and dielectric pillar structures embedded within the substrate-level material layers and located between the memory stack structures.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a tunneling dielectric layer, a vertical semiconductor channel, and a vertical stack of charge storage structures. Each of the charge storage structures includes an annular silicon nitride portion, a lower silicon nitride portion underlying the upper silicon nitride portion, and a spacer located between the upper silicon nitride portion and the lower silicon nitride portion. The upper and lower silicon nitride portions may be charge storage regions, while the spacer may be a floating gate or a dielectric spacer.