Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level. In this case, when none of a plurality of pieces of data is selected using a selection signal, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor of the second dynamic circuit is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: A semiconductor integrated circuit according to the present invention comprises an MOS substrate having a substrate region (MOS) and a source region separated from each other, a dummy MOS circuit substrate-separated from the MOS circuit and having a substrate region (dummy) and a source region (dummy) separated from each other, a substrate voltage generating circuit for generating a substrate voltage to be applied to the substrate region (MOS) and the substrate region (dummy), and a comparing circuit for measuring a current generated in the dummy MOS substrate, wherein an area ratio between the substrate region (dummy) and the source region (dummy) is substantially equal to an area ratio between the substrate region (MOS) and the source region (MOS).

Abstract: Voltage transfer switches and voltage input/output circuits are provided on a complementary bus line pair to be shared among a plurality of columns of a memory cell array. After a complementary bit line pair is precharged to a predetermined voltage, the voltage of uninverted bit line and the voltage of inverted bit line are exchanged before any of all memory cells belonging to the same column is selected by a word line. With this structure, a predetermined potential difference is ensured between the complementary bit line pair at the time of an activation of a sense amplifier even if the total sum of the off-leak currents of access transistors in all the memory cells belonging to the same column is almost as large as the ON-current (drive current) of a single drive transistor.

Abstract: A semiconductor integrated circuit device according to the present invention includes: a sample circuit in which through current to be monitored flows during switching between transistors; a non-overlap circuit for outputting an output signal for the switching in the sample circuit; a current detector for detecting the through current flowing during the switching; and a current comparator in which a reference current value with respect to the through current has been set and which compares a current value detected by the current detector with the reference current value and outputs a result of the comparison to the non-overlap circuit.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.

Abstract: To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data.

Abstract: In a semiconductor integrated circuit, respective semiconductor circuits are disposed in different regions partitioned in accordance with their operation probabilities per unit time, and a supply voltage and a threshold voltage are correlatively controlled in each region. A target value for controlling the threshold voltage is determined in accordance with the operation probability of the semiconductor circuit. A threshold voltage control circuit controls substrate voltages of p-type and n-type MOS transistors included in the semiconductor circuit so that the threshold voltage can be constant at the target value regardless of the temperature change occurring in use. Simultaneously, a supply voltage control circuit controls the supply voltage for the semiconductor circuit so that an objective operating frequency can be attained. As a result, a semiconductor integrated circuit with low power consumption can be obtained.

Abstract: There are provided at least one read word line 15, 16 and 17 for transmitting a read control signal to a memory cell, at least one read bit line 18, 19 and 20 for transmitting information of the memory cell to an outside according to activation of the read control signal corresponding to the read word line, at least one write word line 11 and 12 for transmitting a write control signal to the memory cell, and at least one write bit line 13 and 14 for transmitting external information to the memory cell according to activation of the write control signal corresponding to the write word line, wherein the read bit line and the write bit line are provided as alternately as possible and the read control signal and the write control signal are controlled so as not to be activated at the same time.

Abstract: A semiconductor integrated circuit according to the present invention comprises a circuit as a controlled object including an MOS transistor, wherein a control potential (at least one of a substrate potential and source potential) is to be controlled, a control signal generation circuit for generating a control signal with respect to the control potential based on an internal signal of the circuit as the controlled object, and a control potential control circuit for controlling the control potential (substrate potential/source potential) of the MOS transistor based on the control signal.

Abstract: A semiconductor integrated circuit according to the present invention comprises a latch circuit, a retaining circuit, and a feedback circuit, wherein the latch circuit inputs therein an input data signal, a clock signal and a feedback signal and outputs an output data signal, the retaining circuit retains the output data signal, and the feedback circuit inputs therein the input data signal and the output data signal to thereby generate the feedback signal based on logic combinations of the input data signal and the output data signal, and an internal operation of the latch circuit is turned on/off by means of the feedback signal.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: A method and apparatus for separating and concentrating cells used for regenerating kidney tissues using a simple procedure in a short time is provided. The method comprises introducing a nucleated cells-containing fluid containing cells for kidney regeneration into a filter that can capture nucleated cells without capturing erythrocytes, and introducing a fluid for recovery into the filter, thereby recovering the cells for kidney regeneration captured by the filter. The concentrated cells for kidney regeneration are used for regenerating kidney tissues and treating kidney diseases.

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation.

Abstract: A dynamic semiconductor integrated circuit is provided, in which an operation speed is increased, an operation is stabilized, and low power consumption is realized in a system where a NAND dynamic circuit is connected to a NOR dynamic circuit. A compensating circuit is provided, which compensates for a voltage drop at an output node of the NOR dynamic circuit due to a coupling capacitance formed between the output node of the NOR dynamic circuit and an output node of the NAND dynamic circuit, caused when the output node of the NAND dynamic circuit is discharged while the output node of the NOR dynamic circuit holds a charge.

Abstract: There are provided at least one read word line 15, 16 and 17 for transmitting a read control signal to a memory cell, at least one read bit line 18, 19 and 20 for transmitting information of the memory cell to an outside according to activation of the read control signal corresponding to the read word line, at least one write word line 11 and 12 for transmitting a write control signal to the memory cell, and at least one write bit line 13 and 14 for transmitting external information to the memory cell according to activation of the write control signal corresponding to the write word line, wherein the read bit line and the write bit line are provided as alternately as possible and the read control signal and the write control signal are controlled so as not to be activated at the same time.

Abstract: Each of D flip-flops (FFs) 13a to 13f constituting a scan path circuit has a normal operation input circuit to be selected in a normal operation and a test operation input circuit to be selected in a test operation, and a control signal having an intermediate voltage between a supply voltage and a ground voltage is sent from a voltage generating circuit 17 to the test operation input circuit of each FF in the test operation. In this case, the amount of an output change in data in each FF is smoother than that in the case in which the supply voltage is applied. Consequently, the delay time of the data is increased. The intermediate voltage to be applied to each FF in the test operation is determined based on a feedback signal sent from a test circuit 15 for checking whether scanned-out data have an error or not.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.