Patents by Inventor Masaya Tarui

Masaya Tarui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9471507
    Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 18, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Publication number: 20160284402
    Abstract: According to an embodiment, a memory device includes a nonvolatile memory, a controller, and power storage. The controller is configured to receive, from a host device, a write request for writing data into the nonvolatile memory, and then, write the data based on the write request. The power storage is configured to store power supplied from a power supply. The controller writes, when abnormality in power supplied from the power supply to the memory device is detected, the data based on the write request that has already been received, using the power supplied from the power storage.
    Type: Application
    Filed: January 25, 2016
    Publication date: September 29, 2016
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Masaya Tarui, Yusuke Shirota, Shiyo Yoshimura
  • Publication number: 20160283157
    Abstract: According to an embodiment, a memory device includes a nonvolatile memory and a controller. The controller receives, from a host device, a write request for writing data in the nonvolatile memory, and then performs data writing based on the write request. When a writing order confirmation request, which is issued for confirmation of fact that data writing is performed based on one or more of the write requests that are already sent, is received from the host device, the controller performs data writing based on the write requests received before receiving the writing order confirmation request and then sends to the host device a response with respect to the writing order confirmation request.
    Type: Application
    Filed: February 24, 2016
    Publication date: September 29, 2016
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Masaya Tarui, Yusuke Shirota, Shiyo Yoshimura
  • Patent number: 9430017
    Abstract: According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: August 30, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Kimura, Akihiro Shibata, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Hiroyoshi Haruki, Masaya Tarui, Satoshi Shirai, Yusuke Shirota
  • Patent number: 9423852
    Abstract: According to an embodiment, a power control device includes a storage unit, a monitor, a determining unit, and a controller. The storage device stores a look-up table, which includes relationship between needed power consumptions and start-up conditions of an electronic device including a plurality of modules. The start-up condition of the electronic device is determined from the needed power consumption in the look-up table and specifies a power on/off status of the modules in the electronic device. The monitor monitors a voltage or available power supplied by a power source when the electronic device is activated. The determining unit determines a start-up condition corresponding to needed power consumption, which corresponds to the voltage or available power monitored by the monitor, with reference to the table. The controller sets a start-up condition of the electronic device to start up the electronic device in the start-up condition determined by the determining unit.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Junichi Segawa, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata
  • Patent number: 9417769
    Abstract: A control device according to embodiments may control update of a target region in an electronic paper. The device may comprise a divider unit, a manager unit and an update instruction unit. The divider unit may be configured to divide the target region into a plurality of sub-regions. The manager unit may be configured to configure an update start timing of each sub-region so that flashings occurring at updating of the sub-regions appear at different timings. The update instruction unit may be configured to instruct to execute an update process of each sub-region according to the update start timings.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Akihiro Shibata, Shiyo Yoshimura, Hiroyoshi Haruki
  • Patent number: 9405350
    Abstract: According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Akihiro Shibata, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Hiroyoshi Haruki, Haruhiko Toyama
  • Patent number: 9400753
    Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: July 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
  • Patent number: 9304818
    Abstract: According to an embodiment, a control apparatus for controlling a target device includes an estimation unit and an issuing unit. The estimation unit is configured to estimate a second amount of energy required for the entire system including the target device and the control apparatus until the target device completes an execution of its function that is requested in accordance with an execution request for the target device. The issuing unit is configured to issue a control command for causing the target device to execute its function in accordance with the execution request, when the first amount of energy at a time point of receiving the execution request is greater than the second amount of energy.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: April 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Kimura, Akihiro Shibata, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Hiroyoshi Haruki, Masaya Tarui, Satoshi Shirai, Yusuke Shirota
  • Patent number: 9304578
    Abstract: A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke Shirota, Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Akihiro Shibata
  • Publication number: 20160085292
    Abstract: According to an embodiment, an electronic device includes functional modules and converters. A processor includes a memory storing state information on the state of the processor. Each converter converts the power-supply voltage to a rated voltage for functional modules, and supplies the rated voltage to at least one functional module. When the processor switches to the standby state, a controller stops the supply of the rated voltages to the functional modules except a state holding unit, a receiving unit, and the controller; and stops the operations of the converters not connected to the state holding unit, the receiving unit, and the controller. The state holding unit holds the state information before the processor switches to the standby state. The receiving unit receives a return signal representing the trigger for returning from the standby state. The state holding unit, the receiving unit, and the controller are connected to the same converter.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 24, 2016
    Inventors: Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
  • Publication number: 20160070333
    Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.
    Type: Application
    Filed: November 2, 2015
    Publication date: March 10, 2016
    Inventors: Hiroyoshi Haruki, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Masaya Tarui, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
  • Publication number: 20160020696
    Abstract: According to a power system includes a linear regulator, a step-down switching regulator, and a controller. The linear regulator supplies electrical power to a load. The step-down switching regulator supplies electrical power to the load. Based on input voltage of the linear regulator and the step-down switching regulator and based on load current representing electrical current flowing to the load, the controller performs control to supply electrical power to the load from one of the linear regulator and the switching regulator.
    Type: Application
    Filed: May 11, 2015
    Publication date: January 21, 2016
    Inventors: Akihiro Shibata, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Shiyo Yoshimura
  • Patent number: 9207743
    Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Masaya Tarui, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
  • Publication number: 20150301892
    Abstract: A memory system comprises an encoding processing circuit 100 that performs redundant encoding process on target data Din to be written to thereby generate data RDin such that the number of bits having a predetermined value is half or less than the total number of bits, and a memory 120 to which the data RDin generated by the encoding processing circuit are written.
    Type: Application
    Filed: July 1, 2015
    Publication date: October 22, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaya Tarui, Tatsunori Kanai, Yutaka Yamada
  • Publication number: 20150271817
    Abstract: According to an embodiment, a communication device for dynamically building a network includes a first receiver and a first transmitter. When the communication device attempts to newly join the network, the first receiver waits for reception of a first beacon containing information for joining the network from another communication device already joining the network for a predetermined first period. When the communication device is already joining the network, the first transmitter determines a schedule indicating timings at which a plurality of communication devices already joining the network transmit first beacons so that intervals at which the communication devices transmit the first beacons in the network as a whole do not exceed the first period and transmit the first beacon according to the schedule.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 24, 2015
    Inventors: Masaya Tarui, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura, Tetsuro Kimura, Tatsunori Kanai
  • Publication number: 20150262715
    Abstract: According to an embodiment, an information processing device includes a data obtaining unit and a data storage controller. The data obtaining unit is configured to obtain data measured by a sensor. The data storage controller is configured to store the data obtained by the data obtaining unit in a first memory of volatile nature when a sampling interval indicating an interval at which the data obtaining unit obtains the data is equal to or smaller than a threshold value. The data storage controller is configured to store the data obtained by the data obtaining unit and the data stored in the first memory in a second memory of nonvolatile nature when the sampling interval exceeds the threshold value.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 17, 2015
    Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
  • Publication number: 20150261283
    Abstract: According to an embodiment, a communication device includes a register and a controller. The register receives data from an external device via an input data line. In a first state in which the communication device is able to receive the data, when a condition in which the data is not sent to the input data line continues for a certain period of time, the controller controls to switch state of the communication device to a second state in which power consumption is less than in the first state.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 17, 2015
    Inventors: Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
  • Patent number: 9110667
    Abstract: According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Akihiro Shibata
  • Publication number: 20150228047
    Abstract: A data processing device according to embodiments may comprise: a processor that reconstructs a plurality of update requests for updating at least a part of a display into one or more update requests, or determine that the plurality of the update requests are unnecessary; and an update instruction unit that instructs to execute update processes of the display using the reconstructed one or more update requests.
    Type: Application
    Filed: February 6, 2015
    Publication date: August 13, 2015
    Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Akihiro Shibata