Patents by Inventor Masaya Tarui
Masaya Tarui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9105358Abstract: In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.Type: GrantFiled: June 10, 2011Date of Patent: August 11, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masaya Tarui, Tatsunori Kanai, Yutaka Yamada
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Publication number: 20150212572Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.Type: ApplicationFiled: April 13, 2015Publication date: July 30, 2015Inventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
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Patent number: 9075742Abstract: According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.Type: GrantFiled: January 30, 2012Date of Patent: July 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masaya Tarui, Tatsunori Kanai, Yutaka Yamada, Hideki Yoshida
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Publication number: 20150149711Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.Type: ApplicationFiled: February 4, 2015Publication date: May 28, 2015Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
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Patent number: 9043631Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.Type: GrantFiled: July 24, 2012Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
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Publication number: 20150084892Abstract: A control device according to embodiments may control update of a target region in an electronic paper. The device may comprise a divider unit, a manager unit and an update instruction unit. The divider unit may be configured to divide the target region into a plurality of sub-regions. The manager unit may be configured to configure an update start timing of each sub-region so that flashings occurring at updating of the sub-regions appear at different timings. The update instruction unit may be configured to instruct to execute an update process of each sub-region according to the update start timings.Type: ApplicationFiled: September 11, 2014Publication date: March 26, 2015Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Akihiro Shibata, Shiyo Yoshimura, Hiroyoshi Haruki
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Publication number: 20150089261Abstract: According to an embodiment, an information processing device includes a memory device, one or more peripheral devices, a processor, and a state controller. The processor is able to change between a first state, in which a command is executed, and a second state, in which an interrupt is awaited. When the processor enters the second state and if an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the state controller switches the information processing device to a third state in which power consumption is lower as compared to the first state. If the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the state controller switches the information processing device to a fourth state in which power consumption is lower as compared to the third state.Type: ApplicationFiled: August 27, 2014Publication date: March 26, 2015Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura, Haruhiko Toyama
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Patent number: 8990525Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.Type: GrantFiled: May 6, 2014Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
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Publication number: 20150019895Abstract: According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor.Type: ApplicationFiled: October 2, 2014Publication date: January 15, 2015Inventors: Koichi Fujisaki, Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Akihiro Shibata
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Patent number: 8880914Abstract: According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor.Type: GrantFiled: March 15, 2012Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Fujisaki, Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Akihiro Shibata
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Patent number: 8868952Abstract: According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.Type: GrantFiled: January 9, 2012Date of Patent: October 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyoshi Haruki, Koichi Fujisaki, Satoshi Shirai, Masaya Tarui, Akihiro Shibata, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
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Patent number: 8832335Abstract: According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.Type: GrantFiled: December 22, 2011Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akihiro Shibata, Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki
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Publication number: 20140244916Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.Type: ApplicationFiled: May 6, 2014Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
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Publication number: 20140245039Abstract: According to an embodiment, an information processing apparatus includes: a first control unit to control a first device; and a second control unit to control a second device. The first control unit includes a first request processing unit, a notification unit, and a first execution unit. The second request processing unit receives a second request including an instruction to start a process of the second device. The notification unit notifies the second control unit that the first control unit receives a first request. The second execution unit executes a second request received by the second request processing unit when the first device is in the active state, and executes the second request stored in the storage unit when the notification is received by the notification receiving unit.Type: ApplicationFiled: February 26, 2014Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Yusuke Shirota, Shiyo Yoshimura, Masaya Tarui, Hiroyoshi Haruki, Satoshi Shirai, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama
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Publication number: 20140245045Abstract: According to an embodiment, a control device includes a processor setting unit, a resumption data reading unit, and a resumption processing unit. The processor setting unit is configured to identify, among a plurality of processors included in an information processing system, each of which is connected to one or more memories, a processor connected to a memory storing resumption data for resuming the information processing system and to activate the identified processor, in response to a resumption request for resuming the information processing system from hibernation. The information processing system includes two or more processors each connected with one or more memories. The resumption data reading unit is configured to read the resumption data from the memory that stores the resumption data. The resumption processing unit is configured to resume the information processing system by using the read resumption data.Type: ApplicationFiled: December 10, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyoshi Haruki, Masaya Tarui, Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura, Haruhiko Toyama
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Publication number: 20140240333Abstract: A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory.Type: ApplicationFiled: February 26, 2014Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yusuke Shirota, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Shiyo Yoshimura
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Publication number: 20140245047Abstract: According to an embodiment, an information processing apparatus that includes a processor, has a first control unit, a power storage unit, and a second control unit. The first control unit is configured to control execution of a process by the processor. The power storage unit is configured to store therein power. The second control unit is configured to control reduction of power consumption of the information processing apparatus in a case where there is a process waiting to be executed and an amount of stored power of the power storage unit is equal to or less than a first threshold.Type: ApplicationFiled: December 30, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shiyo Yoshimura, Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Yusuke Shirota, Masaya Tarui, Hiroyoshi Haruki, Satoshi Shirai, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama
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Patent number: 8775752Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.Type: GrantFiled: February 13, 2012Date of Patent: July 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
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Publication number: 20140089715Abstract: According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value.Type: ApplicationFiled: September 19, 2013Publication date: March 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuro Kimura, Akihiro Shibata, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Hiroyoshi Haruki, Masaya Tarui, Satoshi Shirai, Yusuke Shirota
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Patent number: 8683249Abstract: According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. The second memory accepts read and write operations while operating at the third power consumption.Type: GrantFiled: December 5, 2011Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tatsunori Kanai, Yutaka Yamada, Hideki Yoshida, Masaya Tarui