Patents by Inventor Masayoshi Kobayashi
Masayoshi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6854738Abstract: A sealing structure for sealing a gap between a combustor liner having an outer surface and a surrounding structure surrounding the combustor liner, includes: an annular sealing member held on the surrounding structure so as to be in contact with the outer surface of the combustor liner. The sealing member includes a plurality of sealing segments arranged in an annular configuration. The sealing structure seals the gap around the combustor liner of the combustor and absorbs, the difference in thermal expansion between the combustor liner and the surrounding structure.Type: GrantFiled: February 26, 2003Date of Patent: February 15, 2005Assignee: Kawasaki Jukogyo Kabushiki KaishaInventors: Yoshihiro Matsuda, Masayoshi Kobayashi, Takanobu Yoshimura, Hiroaki Miyamoto
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Publication number: 20040255594Abstract: In a control method of a gas turbine engine, an engine controller 4 outputs a combustor power command FD based on an engine condition from an engine condition detector 3. Then, a combustion controller 6 determines each fuel flow rate based on the combustion power command FD. The combustor controller 6 overrides each fuel flow rate for a certain period, to realize smooth stage-process.Type: ApplicationFiled: May 18, 2004Publication date: December 23, 2004Inventors: Makoto Baino, Yukinobu Kouno, Keisuke Sasae, Hideo Kimura, Yasuhiro Kinoshita, Masayoshi Kobayashi, Takanobu Yoshimura
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Patent number: 6803281Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: February 25, 2004Date of Patent: October 12, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Publication number: 20040173394Abstract: In a vehicle for off-road use, an engine is mounted on a lower portion of a body frame, a carburetor is attached to the engine, and a main air cleaner is attached to the carburetor. The carburetor is provided with an air vent unit attached thereto, for transferring atmospheric pressure to fuel in a float chamber in the carburetor, and a supplemental air cleaner is attached to the tip of the air vent unit. The supplemental air cleaner is disposed above the engine, and above and anterior to the carburetor and the main air cleaner. Since the supplemental air cleaner is substantially covered, from below, by the internal combustion engine, the carburetor, and the main air cleaner, fluids splashed up from a road surface can be blocked by these components, so that the supplemental air cleaner is substantially prevented from being exposed to splashed fluids.Type: ApplicationFiled: December 2, 2003Publication date: September 9, 2004Applicant: Honda Motor Co., Ltd.Inventors: Yuuichirou Tsuruta, Masayoshi Kobayashi, Yoshihito Tokuda
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Patent number: 6787817Abstract: The present invention provides a semiconductor device for high frequency application having a high breakdown voltage and the method of manufacturing thereof. A region including a first conductivity type high impurity concentration semiconductor and a region including a first conductivity type low impurity concentration semiconductor are provided from an ohmic layer side at the side far from a semiconductor substrate of the end surface of a barrier layer opposite the semiconductor substrate and between the ohmic layer and a gate electrode. The sheet impurity concentration of the region including a first conductivity type low impurity concentration semiconductor is set to be lower than that between the bottom surface of the gate electrode at the side of the semiconductor substrate and the end surface of the channel layer opposite the semiconductor substrate.Type: GrantFiled: December 13, 2002Date of Patent: September 7, 2004Assignee: Renesas Technology CorporationInventors: Hiroyuki Takazawa, Shinichiro Takatani, Masao Yamane, Masayoshi Kobayashi
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Publication number: 20040166656Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: ApplicationFiled: February 25, 2004Publication date: August 26, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Publication number: 20040159732Abstract: In a magnetic tape apparatus for controlling a running of a magnetic tape to stop at a reference stop position, a control part controls the feed reel shaft and the take-up reel shaft to reel the magnetic tape and a stop position control part displaces a stop position of the magnetic tape from the reference position wherein the control part activates the stop position control part to displace the stop position when the control part stops running the magnetic tape.Type: ApplicationFiled: February 11, 2004Publication date: August 19, 2004Applicant: Fujitsu LimitedInventors: Masayoshi Kobayashi, Masahiko Sakaguchi, Tsuneyoshi Oohara
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Patent number: 6775086Abstract: In a magnetic tape apparatus for controlling a running of a magnetic tape to stop at a reference stop position, a control part controls the feed reel shaft and the take-up reel shaft to reel the magnetic tape and a stop position control part displaces a stop position of the magnetic tape from the reference position wherein the control part activates the stop position control part to displace the stop position when the control part stops running the magnetic tape.Type: GrantFiled: March 28, 2000Date of Patent: August 10, 2004Assignee: Fujitsu LimitedInventors: Masayoshi Kobayashi, Masahiko Sakaguchi, Tsuneyoshi Oohara
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Patent number: 6768739Abstract: A router allowing the entry hit probability of the cache to be increased is disclosed. The cache is searched using a different mask for each cache entry. A maximum or optimum cache prefix length is determined as a length of upper bits of the destination address of the received packet which are not masked by a corresponding mask. Alternatively, the cache is searched using longest prefix match (LFM). A cache entry allowing a plurality of destination addresses to be hit can be registered in the cache, resulting in increased cache hit probability.Type: GrantFiled: February 9, 2000Date of Patent: July 27, 2004Assignee: NEC CorporationInventors: Masayoshi Kobayashi, Tutomu Murase, Hideyuki Shimonishi
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Publication number: 20040130697Abstract: An apparatus for selectively modifying a reflection preventing film formed on a substrate to change the optical characteristic of a region in the reflection preventing film. The apparatus includes: a substrate holding mechanism; a modifying light irradiating mechanism; and a processing position changing mechanism configured to change a processing position of the modifying light on the substrate by changing a relative position between an irradiation position of the modifying light and the substrate held by the substrate holding mechanism.Type: ApplicationFiled: December 16, 2003Publication date: July 8, 2004Applicant: Dainippon Screen Mfg. Co., Ltd.Inventor: Masayoshi Kobayashi
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Patent number: 6720220Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: December 23, 2002Date of Patent: April 13, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Publication number: 20040036230Abstract: A sealing structure for sealing a gap between a combustor liner having an outer surface and a surrounding structure surrounding the combustor liner, includes: an annular sealing member held on the surrounding structure so as to be in contact with the outer surface of the combustor liner. The sealing member includes a plurality of sealing segments arranged in an annular configuration. The sealing structure seals the gap around the combustor liner of the combustor and absorbs, the difference in thermal expansion between the combustor liner and the surrounding structure.Type: ApplicationFiled: February 26, 2003Publication date: February 26, 2004Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHAInventors: Yoshihiro Matsuda, Masayoshi Kobayashi, Takanobu Yoshimura, Hiroaki Miyamoto
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Patent number: 6683741Abstract: A device for receiving a tape cartridge having a reel and a record tape winded around the reel where the record tape has a mounting unit attached to one end thereof includes an engaging unit which engages with the mounting unit, a threader arm which carries the engaging unit together with the mounting unit along a predetermined path to thread the record tape in the device during a threading operation and to unthread the record tape from the device during an unthreading operation, a reel motor which drives the reel of the tape cartridge, and a control unit which controls the reel motor to adjust tension in the record tape during the threading operation and the unthreading operation.Type: GrantFiled: March 24, 2000Date of Patent: January 27, 2004Assignee: Fujitsu LimitedInventors: Masayoshi Kobayashi, Masahiko Sakaguchi, Tsuneyoshi Oohara
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Patent number: 6658853Abstract: A seal structure for sealing a gap between a combustor liner and a neighboring structure adjacent to the combustor liner, includes an annular sealing member mounted on the neighboring structure so as to be in contact with an annular outer surface of the combustor liner to seal the gap between the combustor liner and the neighboring structure. The annular sealing member includes a plurality of sealing segments which are arranged in an annular form as a whole.Type: GrantFiled: July 2, 2002Date of Patent: December 9, 2003Assignee: Kawasaki Jukogyo Kabushiki KaishaInventors: Yoshihiro Matsuda, Masayoshi Kobayashi, Takanobu Yoshimura, Hiroaki Miyamoto
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Publication number: 20030182437Abstract: The stream proxy server of the present invention includes a network information acquisition unit, a transport layer protocol control unit capable of transmitting and receiving data by using a plurality of transport layer protocols having a flow control function and different band sharing characteristics, a reception rate control unit for reading data at a rate determined by the transport layer protocol control unit, and a prefetch control unit for determining a rate of contents acquisition from an origin server and a transport layer protocol to be used based on information obtained from the network information acquisition unit and a buffer margin, and notifying the reception rate control unit of the determined rate and notifying the transport layer protocol control unit of the transport layer protocol to be used.Type: ApplicationFiled: August 28, 2002Publication date: September 25, 2003Applicant: NEC CORPORATIONInventors: Masayoshi Kobayashi, Toshiyasu Kurasugi
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Publication number: 20030168672Abstract: The present invention provides a semiconductor device for high frequency application having a high breakdown voltage and the method of manufacturing thereof. A region including a first conductivity type high impurity concentration semiconductor and a region including a first conductivity type low impurity concentration semiconductor are provided from an ohmic layer side at the side far from a semiconductor substrate of the end surface of a barrier layer opposite the semiconductor substrate and between the ohmic layer and a gate electrode. The sheet impurity concentration of the region including a first conductivity type low impurity concentration semiconductor is set to be lower than that between the bottom surface of the gate electrode at the side of the semiconductor substrate and the end surface of the channel layer opposite the semiconductor substrate.Type: ApplicationFiled: December 13, 2002Publication date: September 11, 2003Inventors: Hiroyuki Takazawa, Shinichiro Takatani, Masao Yamane, Masayoshi Kobayashi
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Publication number: 20030124806Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: ApplicationFiled: December 23, 2002Publication date: July 3, 2003Applicant: Hitachi, Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Publication number: 20030046940Abstract: A seal structure for sealing a gap between a combustor liner and a neighboring structure adjacent to the combustor liner, includes an annular sealing member mounted on the neighboring structure so as to be in contact with an annular outer surface of the combustor liner to seal the gap between the combustor liner and the neighboring structure. The annular sealing member includes a plurality of sealing segments which are arranged in an annular form as a whole.Type: ApplicationFiled: July 2, 2002Publication date: March 13, 2003Applicant: Kawasaki Jukogyo Kabushiki KaishaInventors: Yoshihiro Matsuda, Masayoshi Kobayashi, Takanobu Yoshimura, Hiroaki Miyamoto
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Patent number: 6512265Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: March 27, 2002Date of Patent: January 28, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 6493167Abstract: Disclosed herein is a magnetic tape unit having a magnetic head for reading and writing data from and onto a magnetic tape. The magnetic tape is traveled in contact with the magnetic head during a read/write operation of the magnetic head. During a rest period where the read/write operation of the magnetic head is not performed, a reciprocating motion of the magnetic tape by a small distance is performed with a predetermined period. A temperature in the vicinity of the magnetic head is detected by a temperature sensor. The predetermined period is changed according to the temperature detected by the temperature sensor. Accordingly, the adhesion of the magnetic tape to the magnetic head can be well prevented irrespective of the temperature inside the tape unit.Type: GrantFiled: August 25, 1997Date of Patent: December 10, 2002Assignee: Fujitsu LimitedInventors: Masayoshi Kobayashi, Keisuke Hoshino, Masaru Ohshita, Akira Takano, Makoto Sasaki, Makoto Matsuda, Toshihiko Fujii